An Architectural Design of Process Partitioning and Device Mapping with In-memory Computing for Pedestrian Detection

With the increasing penetration of AI in the field of autonomous driving in recent years, the pedestrian detection system has been receiving more and more attention as an important part of Edge-end applications. The deployment of low-power, high-performance AI computation models at the Edge-end has been a topic of interest for researchers. The in-memory Computing (IMC) paradigm is expected to overcome the problem of frequent data movement between storage and processing modules in traditional Von Neumann-based computation architectures by realizing Multiply-accumulate (MAC) and Matrix-vector Multiplication (MVM) computations directly in memory arrays. However, limited by the scale of the memory arrays of current IMC devices, they can mainly perform only low-precision, small-scale model processing. Therefore, there is a need to quantify the underlying computational architecture of the model and explore efficient means of IMC-based operator partitioning and device mapping. In this paper, we analyze the underlying computational logic of the pedestrian detection system and propose an IMC-based process partitioning and device mapping scheme. We used Field Programmable Gate Array (FPGA) as the assumed IMC devices, performed hardware implementation and system-level verification at lower time and labor costs compared to Complementary Metal Oxide Semiconductor (CMOS) implementations, and analyzed the reliability of the system.