An efficient implementation of hash function processor for IPSEC

Yong Kyu Kang; Dae Won Kim; Taek Won Kwon; Jun Rim Choi

doi:10.1109/APASIC.2002.1031540

An efficient implementation of hash function processor for IPSEC

Yong Kyu Kang, Dae Won Kim, Taek Won Kwon, Jun Rim Choi

School of Electronics Engineering

Kyungpook National University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

41 Scopus citations

Abstract

This paper presents the implementation of hash functions for IPSEC chip. There is an increasing interest in high-speed cryptographic accelerators for IPSec applications such as VPNs (virtual private networks). Because diverse algorithms are used in Internet, various hash algorithms are required for IPSec chip. Therefore, we implemented SHA-IS HAS-160 and MD5 in one chip. These hash algorithms are designed to reduce the number of gates. SHA-I module is combined with HAS-160 module. As the result, the required logic elements are reduced by 27%. These hash algorithms have been implemented using Altera's EP20K1000EBC652-3 with PCI bus interface.

Original language	English
Title of host publication	2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	93-96
Number of pages	4
ISBN (Electronic)	0780373634, 9780780373631
DOIs	https://doi.org/10.1109/APASIC.2002.1031540
State	Published - 2002
Event	3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Taipei, Taiwan, Province of China Duration: 6 Aug 2002 → 8 Aug 2002

Publication series

Name	2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings

Conference

Conference	3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002
Country/Territory	Taiwan, Province of China
City	Taipei
Period	6/08/02 → 8/08/02

Keywords

FPGA
HAS-160
Hash
MD5
SHA-1

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10.1109/APASIC.2002.1031540

Cite this

Kang, Y. K., Kim, D. W., Kwon, T. W., & Choi, J. R. (2002). An efficient implementation of hash function processor for IPSEC. In 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings (pp. 93-96). Article 1031540 (2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APASIC.2002.1031540

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title = "An efficient implementation of hash function processor for IPSEC",

abstract = "This paper presents the implementation of hash functions for IPSEC chip. There is an increasing interest in high-speed cryptographic accelerators for IPSec applications such as VPNs (virtual private networks). Because diverse algorithms are used in Internet, various hash algorithms are required for IPSec chip. Therefore, we implemented SHA-IS HAS-160 and MD5 in one chip. These hash algorithms are designed to reduce the number of gates. SHA-I module is combined with HAS-160 module. As the result, the required logic elements are reduced by 27%. These hash algorithms have been implemented using Altera's EP20K1000EBC652-3 with PCI bus interface.",

keywords = "FPGA, HAS-160, Hash, MD5, SHA-1",

author = "Kang, {Yong Kyu} and Kim, {Dae Won} and Kwon, {Taek Won} and Choi, {Jun Rim}",

note = "Publisher Copyright: {\textcopyright}2002 IEEE.; 3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 ; Conference date: 06-08-2002 Through 08-08-2002",

year = "2002",

doi = "10.1109/APASIC.2002.1031540",

language = "English",

series = "2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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booktitle = "2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings",

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Kang, YK, Kim, DW, Kwon, TW & Choi, JR 2002, An efficient implementation of hash function processor for IPSEC. in 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings., 1031540, 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 93-96, 3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002, Taipei, Taiwan, Province of China, 6/08/02. https://doi.org/10.1109/APASIC.2002.1031540

An efficient implementation of hash function processor for IPSEC. / Kang, Yong Kyu; Kim, Dae Won; Kwon, Taek Won et al.
2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2002. p. 93-96 1031540 (2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - This paper presents the implementation of hash functions for IPSEC chip. There is an increasing interest in high-speed cryptographic accelerators for IPSec applications such as VPNs (virtual private networks). Because diverse algorithms are used in Internet, various hash algorithms are required for IPSec chip. Therefore, we implemented SHA-IS HAS-160 and MD5 in one chip. These hash algorithms are designed to reduce the number of gates. SHA-I module is combined with HAS-160 module. As the result, the required logic elements are reduced by 27%. These hash algorithms have been implemented using Altera's EP20K1000EBC652-3 with PCI bus interface.

AB - This paper presents the implementation of hash functions for IPSEC chip. There is an increasing interest in high-speed cryptographic accelerators for IPSec applications such as VPNs (virtual private networks). Because diverse algorithms are used in Internet, various hash algorithms are required for IPSec chip. Therefore, we implemented SHA-IS HAS-160 and MD5 in one chip. These hash algorithms are designed to reduce the number of gates. SHA-I module is combined with HAS-160 module. As the result, the required logic elements are reduced by 27%. These hash algorithms have been implemented using Altera's EP20K1000EBC652-3 with PCI bus interface.

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An efficient implementation of hash function processor for IPSEC

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Keywords

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