An efficient interworking architecture of a network processor for layer 7 packet processing

This paper presents a new interworking architecture for a network processor (NP) that is able to process packets from OSI layer 2 (L2) to layer 7 (L7) by combining a conventional NP with a general-purpose processor (GP). In general, most commercially available NPs could not afford to support a variety of network services. This is mainly because the conventional NPs are not able to process L7 packets. Thus, one of the most important requirements for the state-of-the-art NP is the ability to process packets of L2 to L7. To process L7 packets efficiently through both the conventional NP and GP, the proposed interworking architecture uses a deep packet inspector (DPI) and it controls the packet processing flow depending on the OSI layers of packets. Experimental results show that the proposed interworking architecture is not only able to process packets of L2 to L7 but also increase the throughput and load balance of the packet processing in the NP without large hardware overhead when compared with the conventional interworking architecture.