An Energy-Efficient Imprecise Adder with a Lower-part Constant Approximation

Hyoju Seo; Yoon Seok Yang; Yongtae Kim

doi:10.1109/ISOCC50952.2020.9332922

An Energy-Efficient Imprecise Adder with a Lower-part Constant Approximation

Hyoju Seo, Yoon Seok Yang, Yongtae Kim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

11 Scopus citations

Abstract

This paper proposes a novel approximate adder that significantly reduces power and energy consumption by leveraging a lower-part constant scheme. When implemented with a 32-nm CMOS technology, the proposed adder reduces area, power, power-delay product, energy-delay product, and area-delay product, respectively, of 43%, 49%, 76%, 89%, and 73% compared to the ripple carry adder that is a traditional precise adder. Also, we demonstrate that our adder design can remarkably reduce power and energy consumption of digital image processing applications while obtaining an acceptable output image quality.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference, ISOCC 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	143-144
Number of pages	2
ISBN (Electronic)	9781728183312
DOIs	https://doi.org/10.1109/ISOCC50952.2020.9332922
State	Published - 21 Oct 2020
Event	17th International System-on-Chip Design Conference, ISOCC 2020 - Yeosu, Korea, Republic of Duration: 21 Oct 2020 → 24 Oct 2020

Publication series

Name	Proceedings - International SoC Design Conference, ISOCC 2020

Conference

Conference	17th International System-on-Chip Design Conference, ISOCC 2020
Country/Territory	Korea, Republic of
City	Yeosu
Period	21/10/20 → 24/10/20

Keywords

approximate adder
approximate computing
energy efficiency
error tolerant adder
imprecise adder
low power

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/ISOCC50952.2020.9332922

Cite this

Seo, H., Yang, Y. S., & Kim, Y. (2020). An Energy-Efficient Imprecise Adder with a Lower-part Constant Approximation. In Proceedings - International SoC Design Conference, ISOCC 2020 (pp. 143-144). Article 9332922 (Proceedings - International SoC Design Conference, ISOCC 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC50952.2020.9332922

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abstract = "This paper proposes a novel approximate adder that significantly reduces power and energy consumption by leveraging a lower-part constant scheme. When implemented with a 32-nm CMOS technology, the proposed adder reduces area, power, power-delay product, energy-delay product, and area-delay product, respectively, of 43\%, 49\%, 76\%, 89\%, and 73\% compared to the ripple carry adder that is a traditional precise adder. Also, we demonstrate that our adder design can remarkably reduce power and energy consumption of digital image processing applications while obtaining an acceptable output image quality.",

keywords = "approximate adder, approximate computing, energy efficiency, error tolerant adder, imprecise adder, low power",

author = "Hyoju Seo and Yang, \{Yoon Seok\} and Yongtae Kim",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 17th International System-on-Chip Design Conference, ISOCC 2020 ; Conference date: 21-10-2020 Through 24-10-2020",

year = "2020",

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doi = "10.1109/ISOCC50952.2020.9332922",

language = "English",

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Seo, H, Yang, YS & Kim, Y 2020, An Energy-Efficient Imprecise Adder with a Lower-part Constant Approximation. in Proceedings - International SoC Design Conference, ISOCC 2020., 9332922, Proceedings - International SoC Design Conference, ISOCC 2020, Institute of Electrical and Electronics Engineers Inc., pp. 143-144, 17th International System-on-Chip Design Conference, ISOCC 2020, Yeosu, Korea, Republic of, 21/10/20. https://doi.org/10.1109/ISOCC50952.2020.9332922

An Energy-Efficient Imprecise Adder with a Lower-part Constant Approximation. / Seo, Hyoju; Yang, Yoon Seok; Kim, Yongtae.
Proceedings - International SoC Design Conference, ISOCC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 143-144 9332922 (Proceedings - International SoC Design Conference, ISOCC 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - This paper proposes a novel approximate adder that significantly reduces power and energy consumption by leveraging a lower-part constant scheme. When implemented with a 32-nm CMOS technology, the proposed adder reduces area, power, power-delay product, energy-delay product, and area-delay product, respectively, of 43%, 49%, 76%, 89%, and 73% compared to the ripple carry adder that is a traditional precise adder. Also, we demonstrate that our adder design can remarkably reduce power and energy consumption of digital image processing applications while obtaining an acceptable output image quality.

AB - This paper proposes a novel approximate adder that significantly reduces power and energy consumption by leveraging a lower-part constant scheme. When implemented with a 32-nm CMOS technology, the proposed adder reduces area, power, power-delay product, energy-delay product, and area-delay product, respectively, of 43%, 49%, 76%, 89%, and 73% compared to the ripple carry adder that is a traditional precise adder. Also, we demonstrate that our adder design can remarkably reduce power and energy consumption of digital image processing applications while obtaining an acceptable output image quality.

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KW - energy efficiency

KW - error tolerant adder

KW - imprecise adder

KW - low power

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BT - Proceedings - International SoC Design Conference, ISOCC 2020

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 17th International System-on-Chip Design Conference, ISOCC 2020

Y2 - 21 October 2020 through 24 October 2020

ER -

An Energy-Efficient Imprecise Adder with a Lower-part Constant Approximation

Abstract

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Conference

Keywords

UN SDGs

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