An experimental 0.8 v 256-kbit SRAM macro with boosted cell array scheme

Yeonbae Chung, Sang Won Shim

Research output: Contribution to journalArticlepeer-review

7 Scopus citations


This work presents a low-voltage static random access memory (SRAM) technique based on a dual-boosted cell array. For each read/write cycle, the wordline and cell power node of selected SRAM cells are boosted into two different voltage levels. This technique enhances the read static noise margin to a sufficient level without an increase in cell size. It also improves the SRAM circuit speed due to an increase in the cell read-out current. A 0.18 μm CMOS 256-kbit SRAM macro is fabricated with the proposed technique, which demonstrates 0.8 V operation with 50 MHz while consuming 65 μW/MHz. It also demonstrates an 87% bit error rate reduction while operating with a 43% higher clock frequency compared with that of conventional SRAM.

Original languageEnglish
Pages (from-to)457-462
Number of pages6
JournalETRI Journal
Issue number4
StatePublished - Aug 2007


  • Booster
  • Memory
  • SRAM
  • Static noise margin


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