@inproceedings{53063edce3754ab1a5652ab92ee24d2e,
title = "An Optimal Design Methodology of Ternary Logic in Iso-device Ternary CMOS",
abstract = "Studies report the possibility of the end of scaling, which is the key engine that has led the era of binary computers. Ternary computing is reported to have one of the highest potential to replace binary computers in the near future. Regarding this forecast, ternary CMOS (T-CMOS) is a device said to be a great candidate. However, research on actual circuit design must follow to verify its advantages fully. Thus, this paper studies the methodologies to design actual ternary logic based on T-CM OS devices. On top of the various novel ternary logic cells that we design, we propose an optimization technique to design arbitrary ternary logic with a minimum number of T-CMOS devices. Enlightening the usefulness of T-CMOS, we implemented a balanced ternary adder using only 68 transistors. Comparing between iso-device designs, we highlight that our ternary adder uses -30.6% fewer transistors than the most compact ternary adder currently-developed.",
keywords = "T-CMOS, ternary adder, ternary logic",
author = "Jonghyun Ko and Kwanwoo Park and Suhyeong Yong and Taegam Jeong and Kim, {Tae Hak} and Taigon Song",
note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 51st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2021 ; Conference date: 25-05-2021 Through 27-05-2021",
year = "2021",
month = may,
doi = "10.1109/ISMVL51352.2021.00040",
language = "English",
series = "Proceedings of The International Symposium on Multiple-Valued Logic",
publisher = "IEEE Computer Society",
pages = "189--194",
booktitle = "Proceedings - 2021 IEEE 51st International Symposium on Multiple-Valued Logic, ISMVL 2021",
address = "United States",
}