@inproceedings{b116c5090f7e43b9afe5ac797abb952a,
title = "An Output-Capacitor-Free Adaptive-Frequency Digital LDO with a 420-mA Load Current and a Fast Settling Time",
abstract = "A typical digital low-dropout regulator (DLDO) that is clocked with a fixed frequency suffers from the trade-offs between power, speed, and stability. This paper proposes a DLDO that achieves both fast settling and low power consumption without limit-cycle oscillation (LCO) by adaptively changing the clock frequency and eventually turning off the clock in the steady state. The proposed LDO also features an inverter-based droop-compensation circuit for output-capacitor-free operation. The proposed LDO designed in a 28-nm CMOS process achieves a 70-ns settling time and a 137-mV droop voltage for the 400-mA load current transition with a 2.6-ns edge time, which translates to the figure of merit of 4.8 fs.",
keywords = "adaptive frequency, Digital low dropout (DLDO) regulator, inverter-based droop-compensation, linear regulator, power management, voltage-controlled oscillator (VCO)",
author = "Min, {Dong Jick} and Lee, {Jun Gi} and Kunhee Cho and Shim, {Jae Hoon}",
note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 56th IEEE International Symposium on Circuits and Systems, ISCAS 2023 ; Conference date: 21-05-2023 Through 25-05-2023",
year = "2023",
doi = "10.1109/ISCAS46773.2023.10182029",
language = "English",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings",
address = "United States",
}