TY - JOUR
T1 - An Output-Capacitor-Free NMOS Digital LDO Using Gate Driving Strength Modulation and Droop Detector
AU - Kim, Jaejin
AU - Koo, Gunmo
AU - Lee, Seongmin
AU - Shim, Jae Hoon
AU - Cho, Kunhee
N1 - Publisher Copyright:
© 2004-2012 IEEE.
PY - 2023/12/1
Y1 - 2023/12/1
N2 - An output-capacitor-free NMOS digital LDO (DLDO) using gate driving strength modulation (GDSM) is described. The proposed DLDO is mainly based on the time-driven topology while the GDSM changes the gate driving level adaptively according to the load current condition. The proposed GDSM lowers the gate driving level in the light load condition which improves the load transient response, widens the load current dynamic range, and reduces the output voltage ripple. A droop detector combined with the modulation scheme is also proposed to further improve the undershoot and recovery time. The proposed DLDO has been implemented in 28 nm CMOS and the 20, 000× load range is obtained even with 256 unity power switch arrays. When the load current changes from 5 mA to 85 mA, the VOUT droop and recovery time are 130 mV and 2.5 μs, which are 4.92× and 70× improvements compared to the baseline time-driven DLDO, respectively.
AB - An output-capacitor-free NMOS digital LDO (DLDO) using gate driving strength modulation (GDSM) is described. The proposed DLDO is mainly based on the time-driven topology while the GDSM changes the gate driving level adaptively according to the load current condition. The proposed GDSM lowers the gate driving level in the light load condition which improves the load transient response, widens the load current dynamic range, and reduces the output voltage ripple. A droop detector combined with the modulation scheme is also proposed to further improve the undershoot and recovery time. The proposed DLDO has been implemented in 28 nm CMOS and the 20, 000× load range is obtained even with 256 unity power switch arrays. When the load current changes from 5 mA to 85 mA, the VOUT droop and recovery time are 130 mV and 2.5 μs, which are 4.92× and 70× improvements compared to the baseline time-driven DLDO, respectively.
KW - Digital LDO
KW - droop detector
KW - dynamic voltage scaling
KW - gate driving strength modulation
KW - wide load dynamic range
UR - http://www.scopus.com/inward/record.url?scp=85165387775&partnerID=8YFLogxK
U2 - 10.1109/TCSI.2023.3293819
DO - 10.1109/TCSI.2023.3293819
M3 - Article
AN - SCOPUS:85165387775
SN - 1549-8328
VL - 70
SP - 4975
EP - 4985
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 12
ER -