Analysis and Compensation of Voltage Distortion by Zero Current Clamping in Voltage-Fed PWM Inverter

Joohn Sheok Kim; Jong Woo Choi; Seung Ki Sul

doi:10.1541/ieejias.117.160

Analysis and Compensation of Voltage Distortion by Zero Current Clamping in Voltage-Fed PWM Inverter

Joohn Sheok Kim, Jong Woo Choi, Seung Ki Sul

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

5 Scopus citations

Abstract

In voltage-fed PWM inverter, the relation between the reference voltage and the output voltage is nonlinear. Especially, when the currents are around zero point, the nonlinear voltage distortion invokes the most serious problems in the system performance. In this paper, the analysis of the voltage distortion by the zero current clamping phenomenon is discussed. From this analysis, a novel distortion voltage compensation strategy that eliminates zero current clamping is presented. Experimental results are also presented to demonstrate the validity of the proposed method.

Original language	English
Pages (from-to)	160-165
Number of pages	6
Journal	IEEJ Transactions on Industry Applications
Volume	117
Issue number	2
DOIs	https://doi.org/10.1541/ieejias.117.160
State	Published - 1997

Keywords

Dead Time
Zero Current Clamping

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10.1541/ieejias.117.160

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title = "Analysis and Compensation of Voltage Distortion by Zero Current Clamping in Voltage-Fed PWM Inverter",

abstract = "In voltage-fed PWM inverter, the relation between the reference voltage and the output voltage is nonlinear. Especially, when the currents are around zero point, the nonlinear voltage distortion invokes the most serious problems in the system performance. In this paper, the analysis of the voltage distortion by the zero current clamping phenomenon is discussed. From this analysis, a novel distortion voltage compensation strategy that eliminates zero current clamping is presented. Experimental results are also presented to demonstrate the validity of the proposed method.",

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AU - Choi, Jong Woo

AU - Sul, Seung Ki

PY - 1997

Y1 - 1997

N2 - In voltage-fed PWM inverter, the relation between the reference voltage and the output voltage is nonlinear. Especially, when the currents are around zero point, the nonlinear voltage distortion invokes the most serious problems in the system performance. In this paper, the analysis of the voltage distortion by the zero current clamping phenomenon is discussed. From this analysis, a novel distortion voltage compensation strategy that eliminates zero current clamping is presented. Experimental results are also presented to demonstrate the validity of the proposed method.

AB - In voltage-fed PWM inverter, the relation between the reference voltage and the output voltage is nonlinear. Especially, when the currents are around zero point, the nonlinear voltage distortion invokes the most serious problems in the system performance. In this paper, the analysis of the voltage distortion by the zero current clamping phenomenon is discussed. From this analysis, a novel distortion voltage compensation strategy that eliminates zero current clamping is presented. Experimental results are also presented to demonstrate the validity of the proposed method.

KW - Dead Time

KW - Zero Current Clamping

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ER -

Analysis and Compensation of Voltage Distortion by Zero Current Clamping in Voltage-Fed PWM Inverter

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Keywords

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