Analysis of source-to-drain capacitance components in tunneling field-effect transistors

this study, small-signal modeling of source-to-drain capacitance (C_sd) in tunneling field-effect transistors (TFETs) was performed for radio-frequency (RF) applications through technology computer-aided design (TCAD) simulation. C_sd is a critical parameter because it affects output impedance matching in RF circuit design. Although the C_sd of a conventional metal-oxide-semiconductor field-effect transistor (MOSFET) is expressed by the channel charge modulation based on the relationship -dQ_s/dv_d, that of a TFET is affected by the distance between the source and the inversion layer edge. Accurate modeling for the admittance at the output port of a TFET was made feasible by inserting an additional capacitive component (Ctunnel) into the RF circuit model. The accuracy of the proposed model was verified by Y₂2 parameters up to 100 GHz.