@inproceedings{32b62bbad5a345abb6bbcf8e5c2258c2,
title = "Architecting large-scale SRAM arrays with monolithic 3D integration",
abstract = "In this paper, we architect large-scale SRAM arrays with monolithic 3D (M3D) integration technology. We introduce M3D-based SRAM arrays with three different ways of integration: M3D-R (vertical routing-only), M3D-VBL (vertical bitline), and M3D-VWL (vertical wordline). We also apply M3D-based SRAM arrays to last-level caches: Tag arrays for eDRAM LLCs and data arrays for SRAM LLCs. The proposed LLCs with M3D-based SRAM arrays lead to better performance and lower energy by 0.02%∼1.7% and 49.1%∼79.1%, respectively, compared to that with TSV-based 3D SRAM arrays.",
keywords = "Energy, Last-Level Caches, Monolithic 3D Integrations, Performance",
author = "Joonho Kong and Gong, {Young Ho} and Chung, {Sung Woo}",
note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 22nd IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017 ; Conference date: 24-07-2017 Through 26-07-2017",
year = "2017",
month = aug,
day = "11",
doi = "10.1109/ISLPED.2017.8009157",
language = "English",
series = "Proceedings of the International Symposium on Low Power Electronics and Design",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "ISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design",
address = "United States",
}