Architecture Design for Pedestrian Detection Based on Memory Grid Occupancy and Data Reuse

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1 Scopus citations

Abstract

Pedestrian Detection, as an integral component of autonomous driving systems, is directly related to the vehicle safety. However, trapped by the current computing paradigm based on Von Neumann architecture, the traditional design of Pedestrian Detection system faces certain dilemmas in terms of energy consumption and computational efficiency. In this paper, an approach based on Memory Grid Occupancy (MGO) and data reuse is proposed to optimize the computational process of the Pedestrian Detection system. The results of the related work indicate that the proposed optimization design in hardware can reduce the data read/write during the execution of the system.

Original languageEnglish
Title of host publication2024 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2024
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350379051
DOIs
StatePublished - 2024
Event2024 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2024 - Okinawa, Japan
Duration: 2 Jul 20245 Jul 2024

Publication series

Name2024 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2024

Conference

Conference2024 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2024
Country/TerritoryJapan
CityOkinawa
Period2/07/245/07/24

Keywords

  • Computing in memory
  • Data Reuse
  • Memory Grid Occupancy
  • Pedestrian Detection
  • Position Detection

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