Atomically Thin 0.65nm and 6nm Vertical Side-Wall MoS2Channel Transistors

Kihan Kim, Byung Chul Jang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Si transistors will face scaling limits below 5 nm due to aggressive short channel effects (SCEs). Two-dimensional (2D) MoS2 semiconductor materials have become attractive for next-generation electronic devices. This study investigated the electrical characteristics of sidewall transistors with a Mos2 channel thickness of 0.65 nm and 6 nm, which is the optimal platform for evaluating SCEs. Furthermore, the conduction mechanism of Mos2 transistor is scrutinized by temperature dependent feature. These results will be a foundation stone for the development of ultra-scaled Mos2transistor.

Original languageEnglish
Title of host publication2023 Silicon Nanoelectronics Workshop, SNW 2023
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages83-84
Number of pages2
ISBN (Electronic)9784863488083
DOIs
StatePublished - 2023
Event26th Silicon Nanoelectronics Workshop, SNW 2023 - Kyoto, Japan
Duration: 11 Jun 202312 Jun 2023

Publication series

Name2023 Silicon Nanoelectronics Workshop, SNW 2023

Conference

Conference26th Silicon Nanoelectronics Workshop, SNW 2023
Country/TerritoryJapan
CityKyoto
Period11/06/2312/06/23

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