Bit-Separable Radix-4 Booth Multiplier for Power-Efficient CNN Accelerator

As the demand for efficient computational hardware escalates, optimizing power-hungry multipliers becomes paramount. This is particularly crucial as high-performance AI applications shift towards low-power edge devices, necessitating reduced power consumption. This paper introduces a novel bit-separable radix-4 Booth multiplier tailored for low-power training and inference on edge device. Our proposed CNN accelerator with bit-separable multiplier maximizes hardware reusability through a structural division of the multiplicand and accelerates speed by first calculating the higher bits of the multiplicand and then decoding the dynamic range of results to omit processing of lower bits. To accommodate various AI models, experiments were conducted using expandable off-chip accelerators. We manufactured an off-chip accelerator chip using the commercial 130nm process. The experimental results showed that compared to the traditional radix-4 Booth multiplier, the chip size was reduced by 18.8%. There was a 68% decrease in total power consumption, a 47% increase in computational speed, and a 53% reduction in computational resources.