@inproceedings{9ef3d49e4c5e4211a6781a09bbcd4363,
title = "Cache Register Sharing Structure for Channel-level Near-memory Processing in NAND Flash Memory",
abstract = "A vast number of data used for Artificial intelligence causes bottleneck between the processor and memory. To tackle this issue, a technology that embeds a processing unit in the memory (PIM: Processing-in Memory) has been proposed. However, SRAM/DRAM based PIM have a issue for lack of capacity. Thus, we propose a NAND flash PIM scheme that shares the cache register. Our scheme significantly reduces the read latency and operation time by -22.8% and -43.7%, compared to the conventional memory system. The power-performance-area (PPA) was reduced by 17.2% by shortening the number of cycles. Our NAND PIM specializes in tasks requiring high-performance computing.",
keywords = "deep neural network, NAND Flash memory, near-Memory processing",
author = "Hyunwoo Kim and Hyundong Lee and Jongbeom Kim and Yunjeong Go and Seungwon Baek and Jaehong Song and Junhyeon Kim and Minyoung Jung and Hyodong Kim and Seongju Kim and Taigon Song",
note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 24th International Symposium on Quality Electronic Design, ISQED 2023 ; Conference date: 05-04-2023 Through 07-04-2023",
year = "2023",
doi = "10.1109/ISQED57927.2023.10129383",
language = "English",
series = "Proceedings - International Symposium on Quality Electronic Design, ISQED",
publisher = "IEEE Computer Society",
booktitle = "Proceedings of the 24th International Symposium on Quality Electronic Design, ISQED 2023",
address = "United States",
}