Characteristics of Conventional STI Process-Related Deep-Level Traps in Silicon

In Man Kang; Hyuck In Kwon; Myung Won Lee; Byung Gook Park; Jong Duk Lee; Sang Sik Park; Jung Chak Ahn; Yong Hee Lee

Characteristics of Conventional STI Process-Related Deep-Level Traps in Silicon

In Man Kang, Hyuck In Kwon, Myung Won Lee, Byung Gook Park, Jong Duk Lee, Sang Sik Park, Jung Chak Ahn, Yong Hee Lee

School of Electronics Engineering

Research output: Contribution to journal › Article › peer-review

5 Scopus citations

Abstract

The deep-level traps in Si substrates caused by the shallow trench isolation (STI) process have been investigated using deep level transient spectroscopy (DLTS). For the DLTS measurements, test patterns consisting of the STI arrays fabricated on p-type epitaxy wafers are proposed. Based on the DLTS measurements, four kinds of deep level traps, which are thought to be related to the STI process, are detected at E _v + 0.16 eV, E _c -0. 23 eV, E _c -0.55 eV, and E _v + 0.58 eV, respectively. The deep levels at E _c -0.55 eV and E _v + 0.58 eV can act as generation-recombination centers. The density of traps was significantly reduced after low-temperature annealing.

Original language	English
Pages (from-to)	69-72
Number of pages	4
Journal	Journal of the Korean Physical Society
Volume	44
Issue number	1
State	Published - Jan 2004

Keywords

Activation energy
Arrhenius plot
Capture cross section
DLTS
Emission rate
Silicon trench etching
STI process

Cite this

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title = "Characteristics of Conventional STI Process-Related Deep-Level Traps in Silicon",

abstract = "The deep-level traps in Si substrates caused by the shallow trench isolation (STI) process have been investigated using deep level transient spectroscopy (DLTS). For the DLTS measurements, test patterns consisting of the STI arrays fabricated on p-type epitaxy wafers are proposed. Based on the DLTS measurements, four kinds of deep level traps, which are thought to be related to the STI process, are detected at E v + 0.16 eV, E c -0. 23 eV, E c -0.55 eV, and E v + 0.58 eV, respectively. The deep levels at E c -0.55 eV and E v + 0.58 eV can act as generation-recombination centers. The density of traps was significantly reduced after low-temperature annealing.",

keywords = "Activation energy, Arrhenius plot, Capture cross section, DLTS, Emission rate, Silicon trench etching, STI process",

author = "Kang, {In Man} and Kwon, {Hyuck In} and Lee, {Myung Won} and Park, {Byung Gook} and Lee, {Jong Duk} and Park, {Sang Sik} and Ahn, {Jung Chak} and Lee, {Yong Hee}",

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T1 - Characteristics of Conventional STI Process-Related Deep-Level Traps in Silicon

AU - Kang, In Man

AU - Kwon, Hyuck In

AU - Lee, Myung Won

AU - Park, Byung Gook

AU - Lee, Jong Duk

AU - Park, Sang Sik

AU - Ahn, Jung Chak

AU - Lee, Yong Hee

PY - 2004/1

Y1 - 2004/1

N2 - The deep-level traps in Si substrates caused by the shallow trench isolation (STI) process have been investigated using deep level transient spectroscopy (DLTS). For the DLTS measurements, test patterns consisting of the STI arrays fabricated on p-type epitaxy wafers are proposed. Based on the DLTS measurements, four kinds of deep level traps, which are thought to be related to the STI process, are detected at E v + 0.16 eV, E c -0. 23 eV, E c -0.55 eV, and E v + 0.58 eV, respectively. The deep levels at E c -0.55 eV and E v + 0.58 eV can act as generation-recombination centers. The density of traps was significantly reduced after low-temperature annealing.

AB - The deep-level traps in Si substrates caused by the shallow trench isolation (STI) process have been investigated using deep level transient spectroscopy (DLTS). For the DLTS measurements, test patterns consisting of the STI arrays fabricated on p-type epitaxy wafers are proposed. Based on the DLTS measurements, four kinds of deep level traps, which are thought to be related to the STI process, are detected at E v + 0.16 eV, E c -0. 23 eV, E c -0.55 eV, and E v + 0.58 eV, respectively. The deep levels at E c -0.55 eV and E v + 0.58 eV can act as generation-recombination centers. The density of traps was significantly reduced after low-temperature annealing.

KW - Activation energy

KW - Arrhenius plot

KW - Capture cross section

KW - DLTS

KW - Emission rate

KW - Silicon trench etching

KW - STI process

UR - http://www.scopus.com/inward/record.url?scp=0842307488&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0842307488

SN - 0374-4884

VL - 44

SP - 69

EP - 72

JO - Journal of the Korean Physical Society

JF - Journal of the Korean Physical Society

IS - 1

ER -

Characteristics of Conventional STI Process-Related Deep-Level Traps in Silicon

Abstract

Keywords

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