Characterization of a Capacitorless DRAM Cell for Cryogenic Memory Applications

Jong Ho Bae; Jong Won Back; Min Woo Kwon; Jae Hwa Seo; Keon Yoo; Sung Yun Woo; Kyungchul Park; Byung Gook Park; Jong Ho Lee

doi:10.1109/LED.2019.2933504

Characterization of a Capacitorless DRAM Cell for Cryogenic Memory Applications

Jong Ho Bae, Jong Won Back, Min Woo Kwon, Jae Hwa Seo, Keon Yoo, Sung Yun Woo, Kyungchul Park, Byung Gook Park, Jong Ho Lee

School of Electronics Engineering

Research output: Contribution to journal › Article › peer-review

15 Scopus citations

Abstract

A partially depleted silicon-on-insulator MOSFET is analyzed over a wide temperature range from 380K to 80K to characterize memory performance at cryogenic temperatures and verify its feasibility as a cryogenic memory cell. In the Shockley-Read-Hall theory, the generation-recombination rate decreases with decreasing temperature, therefore, the retention properties of the capacitorless single transistor DRAM cell are greatly improved as temperature decreases. The static and dynamic retention times increase sharply as temperature decreases. The dynamic retention time reaches up to 3.5 s at 80K, which is 10⁴ times larger than that at 300K. In addition, as the temperature decreases, the current sensing margin also increases more than 2.5 times at 80K (∼ 11 μA) compared to that at 300K, due to the improved dynamic retention characteristics and the increased transconductance.

Original language	English
Article number	8789468
Pages (from-to)	1614-1617
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	40
Issue number	10
DOIs	https://doi.org/10.1109/LED.2019.2933504
State	Published - Oct 2019

Keywords

1T-DRAM
Capacitor-less DRAM
cryogenic memory
MOSFET
PDSOI

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10.1109/LED.2019.2933504

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title = "Characterization of a Capacitorless DRAM Cell for Cryogenic Memory Applications",

abstract = "A partially depleted silicon-on-insulator MOSFET is analyzed over a wide temperature range from 380K to 80K to characterize memory performance at cryogenic temperatures and verify its feasibility as a cryogenic memory cell. In the Shockley-Read-Hall theory, the generation-recombination rate decreases with decreasing temperature, therefore, the retention properties of the capacitorless single transistor DRAM cell are greatly improved as temperature decreases. The static and dynamic retention times increase sharply as temperature decreases. The dynamic retention time reaches up to 3.5 s at 80K, which is 104 times larger than that at 300K. In addition, as the temperature decreases, the current sensing margin also increases more than 2.5 times at 80K (∼ 11 μA) compared to that at 300K, due to the improved dynamic retention characteristics and the increased transconductance.",

keywords = "1T-DRAM, Capacitor-less DRAM, cryogenic memory, MOSFET, PDSOI",

author = "Bae, {Jong Ho} and Back, {Jong Won} and Kwon, {Min Woo} and Seo, {Jae Hwa} and Keon Yoo and Woo, {Sung Yun} and Kyungchul Park and Park, {Byung Gook} and Lee, {Jong Ho}",

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year = "2019",

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doi = "10.1109/LED.2019.2933504",

language = "English",

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AU - Bae, Jong Ho

AU - Back, Jong Won

AU - Kwon, Min Woo

AU - Seo, Jae Hwa

AU - Yoo, Keon

AU - Woo, Sung Yun

AU - Park, Kyungchul

AU - Park, Byung Gook

AU - Lee, Jong Ho

PY - 2019/10

Y1 - 2019/10

N2 - A partially depleted silicon-on-insulator MOSFET is analyzed over a wide temperature range from 380K to 80K to characterize memory performance at cryogenic temperatures and verify its feasibility as a cryogenic memory cell. In the Shockley-Read-Hall theory, the generation-recombination rate decreases with decreasing temperature, therefore, the retention properties of the capacitorless single transistor DRAM cell are greatly improved as temperature decreases. The static and dynamic retention times increase sharply as temperature decreases. The dynamic retention time reaches up to 3.5 s at 80K, which is 104 times larger than that at 300K. In addition, as the temperature decreases, the current sensing margin also increases more than 2.5 times at 80K (∼ 11 μA) compared to that at 300K, due to the improved dynamic retention characteristics and the increased transconductance.

AB - A partially depleted silicon-on-insulator MOSFET is analyzed over a wide temperature range from 380K to 80K to characterize memory performance at cryogenic temperatures and verify its feasibility as a cryogenic memory cell. In the Shockley-Read-Hall theory, the generation-recombination rate decreases with decreasing temperature, therefore, the retention properties of the capacitorless single transistor DRAM cell are greatly improved as temperature decreases. The static and dynamic retention times increase sharply as temperature decreases. The dynamic retention time reaches up to 3.5 s at 80K, which is 104 times larger than that at 300K. In addition, as the temperature decreases, the current sensing margin also increases more than 2.5 times at 80K (∼ 11 μA) compared to that at 300K, due to the improved dynamic retention characteristics and the increased transconductance.

KW - 1T-DRAM

KW - Capacitor-less DRAM

KW - cryogenic memory

KW - MOSFET

KW - PDSOI

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JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

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ER -

Characterization of a Capacitorless DRAM Cell for Cryogenic Memory Applications

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Keywords

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