CMOS-Compatible Low-Power Gated Diode Synaptic Device for Hardware- Based Neural Network

Min Kyu Park; Ho Nam Yoo; Joon Hwang; Sung Yun Woo; Dongseok Kwon; Young Tak Seo; Jong Ho Lee; Jong Ho Bae

doi:10.1109/TED.2021.3134601

CMOS-Compatible Low-Power Gated Diode Synaptic Device for Hardware- Based Neural Network

Min Kyu Park
, Ho Nam Yoo
, Joon Hwang
, Sung Yun Woo
, Dongseok Kwon
, Young Tak Seo
, Jong Ho Lee
, Jong Ho Bae

School of Electronics Engineering

Research output: Contribution to journal › Article › peer-review

6 Scopus citations

Abstract

A gated diode with a charge trap insulator stack (Al2O3/Si3N4/SiO2) is proposed as a synaptic device and its potentiation and depression operations have been demonstrated. Using the band-to-band tunneling current, the gated diode operates with low current (in nanoampere range) and is suitable for low-power hardware-based neural networks. Since the proposed device has merits on simple and compact structure (half of a MOSFET) and compatibility with conventional CMOS technology, integration with CMOS peripheral circuits including neuron circuits and driving IC is possible.

Original language	English
Pages (from-to)	832-837
Number of pages	6
Journal	IEEE Transactions on Electron Devices
Volume	69
Issue number	2
DOIs	https://doi.org/10.1109/TED.2021.3134601
State	Published - 1 Feb 2022

Keywords

Band-to-band current
charge trap memory
low power
synaptic device

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10.1109/TED.2021.3134601

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title = "CMOS-Compatible Low-Power Gated Diode Synaptic Device for Hardware- Based Neural Network",

abstract = "A gated diode with a charge trap insulator stack (Al2O3/Si3N4/SiO2) is proposed as a synaptic device and its potentiation and depression operations have been demonstrated. Using the band-to-band tunneling current, the gated diode operates with low current (in nanoampere range) and is suitable for low-power hardware-based neural networks. Since the proposed device has merits on simple and compact structure (half of a MOSFET) and compatibility with conventional CMOS technology, integration with CMOS peripheral circuits including neuron circuits and driving IC is possible.",

keywords = "Band-to-band current, charge trap memory, low power, synaptic device",

author = "Park, \{Min Kyu\} and Yoo, \{Ho Nam\} and Joon Hwang and Woo, \{Sung Yun\} and Dongseok Kwon and Seo, \{Young Tak\} and Lee, \{Jong Ho\} and Bae, \{Jong Ho\}",

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AU - Park, Min Kyu

AU - Yoo, Ho Nam

AU - Hwang, Joon

AU - Woo, Sung Yun

AU - Kwon, Dongseok

AU - Seo, Young Tak

AU - Lee, Jong Ho

AU - Bae, Jong Ho

PY - 2022/2/1

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N2 - A gated diode with a charge trap insulator stack (Al2O3/Si3N4/SiO2) is proposed as a synaptic device and its potentiation and depression operations have been demonstrated. Using the band-to-band tunneling current, the gated diode operates with low current (in nanoampere range) and is suitable for low-power hardware-based neural networks. Since the proposed device has merits on simple and compact structure (half of a MOSFET) and compatibility with conventional CMOS technology, integration with CMOS peripheral circuits including neuron circuits and driving IC is possible.

AB - A gated diode with a charge trap insulator stack (Al2O3/Si3N4/SiO2) is proposed as a synaptic device and its potentiation and depression operations have been demonstrated. Using the band-to-band tunneling current, the gated diode operates with low current (in nanoampere range) and is suitable for low-power hardware-based neural networks. Since the proposed device has merits on simple and compact structure (half of a MOSFET) and compatibility with conventional CMOS technology, integration with CMOS peripheral circuits including neuron circuits and driving IC is possible.

KW - Band-to-band current

KW - charge trap memory

KW - low power

KW - synaptic device

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JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

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ER -

CMOS-Compatible Low-Power Gated Diode Synaptic Device for Hardware- Based Neural Network

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Keywords

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