CMOS latch bit-cell array for low-power SRAM design

Yeonbae Chung, Weijie Cheng

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

The design and physical implementation of a low-power SRAM with 4T CMOS latch bit-cell is presented. The memory cells in this work are composed of two cross-coupled inverters without any access transistors. They are accessed by totally novel read and write methods that result in low operating power dissipation in the nature. A 1.8V SRAM test chip has been fabricated in a 0.18 μm CMOS technology, which demonstrated the functionality of the memory cell. This new SRAM operates with 30% reduction in read power and 42% reduction in write power compared to the standard 6T SRAM.

Original languageEnglish
Pages (from-to)1145-1151
Number of pages7
JournalIEICE Electronics Express
Volume7
Issue number15
DOIs
StatePublished - 10 Aug 2010

Keywords

  • 4-transistor cell
  • Embedded memory
  • Low-power
  • SRAM

Fingerprint

Dive into the research topics of 'CMOS latch bit-cell array for low-power SRAM design'. Together they form a unique fingerprint.

Cite this