Corea: Delay-and energy-efficient approximate adder using effective carry speculation

Hyelin Seok, Hyoju Seo, Jungwon Lee, Yongtae Kim

Research output: Contribution to journalArticlepeer-review

12 Scopus citations

Abstract

This paper presents a delay-and energy-efficient approximate adder design exploiting an effective carry speculation scheme with error reduction. The proposed scheme reduces the delay and improves the energy efficiency without any significant accuracy degradation by effectively adding the predicted carry input using the OR operation. Additionally, the error reduction technique improves the overall computation accuracy at the expense of a few logic gates. As a result, the proposed adder achieves 3.84-and 7.79-times greater energy and energy-delay product (EDP) efficiencies than the traditional adder when implemented in 65-nm CMOS technology. In particular, when jointly analyzed with hardware accuracy, our design attains 69% and 70% reductions of the energy-and EDP-normalized mean error distance (NMED) products, respectively, compared to the other approximate adders under consideration. Furthermore, the proposed adder’s efficacy over the existing adders is demonstrated by adopting it in a machine learning application.

Original languageEnglish
Article number2234
JournalElectronics (Switzerland)
Volume10
Issue number18
DOIs
StatePublished - Sep 2021

Keywords

  • Approximate adder
  • Approximate circuit
  • Approximate computing
  • Arithmetic circuit
  • Carry speculation
  • Energy-efficiency
  • Error reduction
  • Low-power

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