Damage-free SiO2/SiNx side-wall gate process and its application to 40nm InGaAs/InAIAs HEMT's with 65% InGaAs channel

Dae Hyun Kim; Suk Jin Kim; Young Ho Kim; Kwang Seok Seo

Damage-free SiO₂/SiN_x side-wall gate process and its application to 40nm InGaAs/InAIAs HEMT's with 65% InGaAs channel

Dae Hyun Kim, Suk Jin Kim, Young Ho Kim, Kwang Seok Seo

Seoul National University

Research output: Contribution to journal › Conference article › peer-review

3 Scopus citations

Abstract

Highly reproducible side-wall process for the fabrication of the fine gate length as small as 40nm was developed. This process was utilized to fabricate 40nm InGaAs HEMTs with the 65% strained channel. With the usage of the dual SiO₂ and SiN_x dielectric layers and the proper selection of the etching gas, the final gate length (L_g) was insensitive to the process conditions such as the dielectric over-etching time. From the microwave measurement up to 40GHz, extrapolated f_T and f_max as high as 371 and 345 GHz were obtained, respectively. We believe that the developed side-wall process would be directly applicable to finer gate fabrication, if the initial line length is lessened below the 100nm range.

Original language	English
Pages (from-to)	61-64
Number of pages	4
Journal	Conference Proceedings - International Conference on Indium Phosphide and Related Materials
State	Published - 2003
Event	2003 International Conference Indium Phosphide and Related Materials - Santa Barbara, CA, United States Duration: 12 May 2003 → 16 May 2003

Cite this

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title = "Damage-free SiO2/SiNx side-wall gate process and its application to 40nm InGaAs/InAIAs HEMT's with 65% InGaAs channel",

abstract = "Highly reproducible side-wall process for the fabrication of the fine gate length as small as 40nm was developed. This process was utilized to fabricate 40nm InGaAs HEMTs with the 65% strained channel. With the usage of the dual SiO2 and SiNx dielectric layers and the proper selection of the etching gas, the final gate length (Lg) was insensitive to the process conditions such as the dielectric over-etching time. From the microwave measurement up to 40GHz, extrapolated fT and fmax as high as 371 and 345 GHz were obtained, respectively. We believe that the developed side-wall process would be directly applicable to finer gate fabrication, if the initial line length is lessened below the 100nm range.",

author = "Kim, {Dae Hyun} and Kim, {Suk Jin} and Kim, {Young Ho} and Seo, {Kwang Seok}",

year = "2003",

language = "English",

pages = "61--64",

journal = "Conference Proceedings - International Conference on Indium Phosphide and Related Materials",

issn = "1092-8669",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2003 International Conference Indium Phosphide and Related Materials ; Conference date: 12-05-2003 Through 16-05-2003",

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T1 - Damage-free SiO2/SiNx side-wall gate process and its application to 40nm InGaAs/InAIAs HEMT's with 65% InGaAs channel

AU - Kim, Dae Hyun

AU - Kim, Suk Jin

AU - Kim, Young Ho

AU - Seo, Kwang Seok

PY - 2003

Y1 - 2003

N2 - Highly reproducible side-wall process for the fabrication of the fine gate length as small as 40nm was developed. This process was utilized to fabricate 40nm InGaAs HEMTs with the 65% strained channel. With the usage of the dual SiO2 and SiNx dielectric layers and the proper selection of the etching gas, the final gate length (Lg) was insensitive to the process conditions such as the dielectric over-etching time. From the microwave measurement up to 40GHz, extrapolated fT and fmax as high as 371 and 345 GHz were obtained, respectively. We believe that the developed side-wall process would be directly applicable to finer gate fabrication, if the initial line length is lessened below the 100nm range.

AB - Highly reproducible side-wall process for the fabrication of the fine gate length as small as 40nm was developed. This process was utilized to fabricate 40nm InGaAs HEMTs with the 65% strained channel. With the usage of the dual SiO2 and SiNx dielectric layers and the proper selection of the etching gas, the final gate length (Lg) was insensitive to the process conditions such as the dielectric over-etching time. From the microwave measurement up to 40GHz, extrapolated fT and fmax as high as 371 and 345 GHz were obtained, respectively. We believe that the developed side-wall process would be directly applicable to finer gate fabrication, if the initial line length is lessened below the 100nm range.

UR - http://www.scopus.com/inward/record.url?scp=0038487284&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0038487284

SN - 1092-8669

SP - 61

EP - 64

JO - Conference Proceedings - International Conference on Indium Phosphide and Related Materials

JF - Conference Proceedings - International Conference on Indium Phosphide and Related Materials

T2 - 2003 International Conference Indium Phosphide and Related Materials

Y2 - 12 May 2003 through 16 May 2003

ER -

Damage-free SiO₂/SiN_x side-wall gate process and its application to 40nm InGaAs/InAIAs HEMT's with 65% InGaAs channel

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