TY - JOUR
T1 - DCPA
T2 - approximate adder design exploiting dual carry prediction
AU - Choi, Woong
AU - Shim, Minseob
AU - Seok, Hyelin
AU - Kim, Yongtae
N1 - Publisher Copyright:
1 Copyright © 2021 The Institute of Electronics, Information and Communication Engineers
PY - 2021/12/10
Y1 - 2021/12/10
N2 - This letter presents a novel approximate adder that significantly improves computation accuracy by utilizing a dual carry prediction and error reduction scheme. In our experiments, the proposed adder improves mean error distance (MED) and mean relative error distance (MRED) by up to 58.6% and 58.5%, respectively, when compared with existing approximate adders. Also, when implemented in 65-nm CMOS technology, the proposed adder reduces area, delay, and power by 37%, 48%, and 41%, respectively, compared with the traditional adder. Furthermore, the effectiveness of our design over existing adders is investigated using a digital image processing application.
AB - This letter presents a novel approximate adder that significantly improves computation accuracy by utilizing a dual carry prediction and error reduction scheme. In our experiments, the proposed adder improves mean error distance (MED) and mean relative error distance (MRED) by up to 58.6% and 58.5%, respectively, when compared with existing approximate adders. Also, when implemented in 65-nm CMOS technology, the proposed adder reduces area, delay, and power by 37%, 48%, and 41%, respectively, compared with the traditional adder. Furthermore, the effectiveness of our design over existing adders is investigated using a digital image processing application.
KW - Approximate adder
KW - Dual carry prediction
KW - Energy efficiency
UR - http://www.scopus.com/inward/record.url?scp=85122635232&partnerID=8YFLogxK
U2 - 10.1587/elex.18.20210431
DO - 10.1587/elex.18.20210431
M3 - Article
AN - SCOPUS:85122635232
SN - 1349-2543
VL - 18
JO - IEICE Electronics Express
JF - IEICE Electronics Express
IS - 23
ER -