Demonstration of low power 3-bit multilevel cell characteristics in a TaO_x-Based RRAM by stack engineering

Multilevel cell (MLC) storage technology is attractive in achieving ultrahigh density memory with low cost. In this letter, we have demonstrated 3-bit per cell storage characteristics in a TaO_x-based RRAM. By analyzing the key requirements for MLC operation mainly the switching uniformity and stability of resistance levels, an engineered stack based on thermodynamics in top electrode/(vacancy reservoir/defect control layer)/switching layer/bottom electrode structure was designed. In the optimized stack with ∼ 10-nm Ta layer incorporated at W/TaO_x interface, seven low resistance state levels with same high resistance state were obtained by controlling the switching current down from 30~μ A enabling low power 3-bit storage in contrast to the control device which shows 2-bit MLC with resistance saturation. The improved switching and MLC behavior is attributed to the minimized stochastic nature of set/reset operations due to filament confinement by favorable electric field generation and formation of thin but highly conductive filament which is confirmed electrically.