@inproceedings{9912fe3132ed4c3badcd3d865899607c,
title = "Design and analysis of 3D IC-based low power stereo matching processors",
abstract = "This paper presents comprehensive design and analysis results of 3D IC-based low-power stereo matching processors. Our design efforts range from architecture design and verification to RTL-to-GDSII design and sign-off analysis based on GlobalFoundries 130-nm PDK. We conduct comprehensive studies on the area, performance, and power benefits of our 3D IC designs over 2D IC designs. Our 2-tier 3D IC designs attain 43% area, 14% wire length, and 13% power saving over 2D IC designs. We also study a pipeline-based partitioning method shown to be effective at minimizing power consumption and the total number of TSVs while balancing the size of each tier.",
keywords = "3D IC, low-power design, Stereo matching processor, TSV",
author = "Ok, {Seung Ho} and Bae, {Kyeong Ryeol} and Lim, {Sung Kyu} and Byungin Moon",
year = "2013",
doi = "10.1109/ISLPED.2013.6629260",
language = "English",
isbn = "9781479912353",
series = "Proceedings of the International Symposium on Low Power Electronics and Design",
pages = "15--20",
booktitle = "Proceedings of the International Symposium on Low Power Electronics and Design, ISLPED 2013",
note = "2013 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2013 ; Conference date: 04-09-2013 Through 06-09-2013",
}