Design and analysis of 3D-MAPS (3D Massively parallel processor with stacked memory)

Dae Hyun Kim; Krit Athikulwongse; Michael B. Healy; Mohammad M. Hossain; Moongon Jung; Ilya Khorosh; Gokul Kumar; Young Joon Lee; Dean L. Lewis; Tzu Wei Lin; Chang Liu; Shreepad Panth; Mohit Pathak; Minzhen Ren; Guanhao Shen; Taigon Song; Dong Hyuk Woo; Xin Zhao; Joungho Kim; Ho Choi; Gabriel H. Loh; Hsien Hsin S. Lee; Sung Kyu Lim

doi:10.1109/TC.2013.192

Design and analysis of 3D-MAPS (3D Massively parallel processor with stacked memory)

Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young Joon Lee, Dean L. Lewis, Tzu Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho ChoiGabriel H. Loh, Hsien Hsin S. Lee, Sung Kyu Lim

School of Electronics Engineering

Research output: Contribution to journal › Article › peer-review

55 Scopus citations

Abstract

This paper describes the architecture, design, analysis, and simulation and measurement results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built with a 1.5 V, 130 nm process technology and a two-tier 3D stacking technology using 1.2 μm-diameter, 6 μm-height through-silicon vias (TSVs) and 3.4\nbspμm-diameter face-to-face bond pads. 3D-MAPS consists of a core tier containing 64 cores and a memory tier containing 64 memory blocks. Each core communicates with its dedicated 4KB SRAM block using face-to-face bond pads, which provide negligible data transfer delay between the core and the memory tiers. The maximum operating frequency is 277 MHz and the maximum memory bandwidth is 70.9 GB/s at 277 MHz. The peak measured memory bandwidth usage is 63.8 GB/s and the peak measured power is approximately 4 W based on eight parallel benchmarks.

Original language	English
Article number	6616546
Pages (from-to)	112-125
Number of pages	14
Journal	IEEE Transactions on Computers
Volume	64
Issue number	1
DOIs	https://doi.org/10.1109/TC.2013.192
State	Published - 1 Jan 2015

Keywords

3D integrated circuits
3D Multiprocessor-memory stacked systems
Computer-aided design
RTL implementation and simulation

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10.1109/TC.2013.192

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Kim, D. H., Athikulwongse, K., Healy, M. B., Hossain, M. M., Jung, M., Khorosh, I., Kumar, G., Lee, Y. J., Lewis, D. L., Lin, T. W., Liu, C., Panth, S., Pathak, M., Ren, M., Shen, G., Song, T., Woo, D. H., Zhao, X., Kim, J., ... Lim, S. K. (2015). Design and analysis of 3D-MAPS (3D Massively parallel processor with stacked memory). IEEE Transactions on Computers, 64(1), 112-125. Article 6616546. https://doi.org/10.1109/TC.2013.192

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title = "Design and analysis of 3D-MAPS (3D Massively parallel processor with stacked memory)",

abstract = "This paper describes the architecture, design, analysis, and simulation and measurement results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built with a 1.5 V, 130 nm process technology and a two-tier 3D stacking technology using 1.2 μm-diameter, 6 μm-height through-silicon vias (TSVs) and 3.4\nbspμm-diameter face-to-face bond pads. 3D-MAPS consists of a core tier containing 64 cores and a memory tier containing 64 memory blocks. Each core communicates with its dedicated 4KB SRAM block using face-to-face bond pads, which provide negligible data transfer delay between the core and the memory tiers. The maximum operating frequency is 277 MHz and the maximum memory bandwidth is 70.9 GB/s at 277 MHz. The peak measured memory bandwidth usage is 63.8 GB/s and the peak measured power is approximately 4 W based on eight parallel benchmarks.",

keywords = "3D integrated circuits, 3D Multiprocessor-memory stacked systems, Computer-aided design, RTL implementation and simulation",

author = "Kim, {Dae Hyun} and Krit Athikulwongse and Healy, {Michael B.} and Hossain, {Mohammad M.} and Moongon Jung and Ilya Khorosh and Gokul Kumar and Lee, {Young Joon} and Lewis, {Dean L.} and Lin, {Tzu Wei} and Chang Liu and Shreepad Panth and Mohit Pathak and Minzhen Ren and Guanhao Shen and Taigon Song and Woo, {Dong Hyuk} and Xin Zhao and Joungho Kim and Ho Choi and Loh, {Gabriel H.} and Lee, {Hsien Hsin S.} and Lim, {Sung Kyu}",

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year = "2015",

month = jan,

day = "1",

doi = "10.1109/TC.2013.192",

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Kim, DH, Athikulwongse, K, Healy, MB, Hossain, MM, Jung, M, Khorosh, I, Kumar, G, Lee, YJ, Lewis, DL, Lin, TW, Liu, C, Panth, S, Pathak, M, Ren, M, Shen, G, Song, T, Woo, DH, Zhao, X, Kim, J, Choi, H, Loh, GH, Lee, HHS & Lim, SK 2015, 'Design and analysis of 3D-MAPS (3D Massively parallel processor with stacked memory)', IEEE Transactions on Computers, vol. 64, no. 1, 6616546, pp. 112-125. https://doi.org/10.1109/TC.2013.192

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T1 - Design and analysis of 3D-MAPS (3D Massively parallel processor with stacked memory)

AU - Kim, Dae Hyun

AU - Athikulwongse, Krit

AU - Healy, Michael B.

AU - Hossain, Mohammad M.

AU - Jung, Moongon

AU - Khorosh, Ilya

AU - Kumar, Gokul

AU - Lee, Young Joon

AU - Lewis, Dean L.

AU - Lin, Tzu Wei

AU - Liu, Chang

AU - Panth, Shreepad

AU - Pathak, Mohit

AU - Ren, Minzhen

AU - Shen, Guanhao

AU - Song, Taigon

AU - Woo, Dong Hyuk

AU - Zhao, Xin

AU - Kim, Joungho

AU - Choi, Ho

AU - Loh, Gabriel H.

AU - Lee, Hsien Hsin S.

AU - Lim, Sung Kyu

PY - 2015/1/1

Y1 - 2015/1/1

N2 - This paper describes the architecture, design, analysis, and simulation and measurement results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built with a 1.5 V, 130 nm process technology and a two-tier 3D stacking technology using 1.2 μm-diameter, 6 μm-height through-silicon vias (TSVs) and 3.4\nbspμm-diameter face-to-face bond pads. 3D-MAPS consists of a core tier containing 64 cores and a memory tier containing 64 memory blocks. Each core communicates with its dedicated 4KB SRAM block using face-to-face bond pads, which provide negligible data transfer delay between the core and the memory tiers. The maximum operating frequency is 277 MHz and the maximum memory bandwidth is 70.9 GB/s at 277 MHz. The peak measured memory bandwidth usage is 63.8 GB/s and the peak measured power is approximately 4 W based on eight parallel benchmarks.

AB - This paper describes the architecture, design, analysis, and simulation and measurement results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built with a 1.5 V, 130 nm process technology and a two-tier 3D stacking technology using 1.2 μm-diameter, 6 μm-height through-silicon vias (TSVs) and 3.4\nbspμm-diameter face-to-face bond pads. 3D-MAPS consists of a core tier containing 64 cores and a memory tier containing 64 memory blocks. Each core communicates with its dedicated 4KB SRAM block using face-to-face bond pads, which provide negligible data transfer delay between the core and the memory tiers. The maximum operating frequency is 277 MHz and the maximum memory bandwidth is 70.9 GB/s at 277 MHz. The peak measured memory bandwidth usage is 63.8 GB/s and the peak measured power is approximately 4 W based on eight parallel benchmarks.

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KW - 3D Multiprocessor-memory stacked systems

KW - Computer-aided design

KW - RTL implementation and simulation

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DO - 10.1109/TC.2013.192

M3 - Article

AN - SCOPUS:84919496667

SN - 0018-9340

VL - 64

SP - 112

EP - 125

JO - IEEE Transactions on Computers

JF - IEEE Transactions on Computers

IS - 1

M1 - 6616546

ER -

Design and analysis of 3D-MAPS (3D Massively parallel processor with stacked memory)

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Keywords

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