TY - GEN
T1 - Design and analysis of a low-power ternary SRAM
AU - Choi, Youngchang
AU - Kim, Sunmean
AU - Lee, Kyongsu
AU - Kang, Seokhyeong
N1 - Publisher Copyright:
© 2021 IEEE
PY - 2021
Y1 - 2021
N2 - This paper proposes the design of a ternary inverter that uses low current as input voltage is VDD/2. When the supply voltage is set to 1 V, current supplied by a voltage source as an input voltage VDD/2 is reduced by 22.75% from 1.89µA to 1.46µA. By connecting ternary inverters back-to-back, a tritstorage element is implemented as a ternary SRAM cell. This paper also presents the first verification of read/write schemes that consider noise margins.
AB - This paper proposes the design of a ternary inverter that uses low current as input voltage is VDD/2. When the supply voltage is set to 1 V, current supplied by a voltage source as an input voltage VDD/2 is reduced by 22.75% from 1.89µA to 1.46µA. By connecting ternary inverters back-to-back, a tritstorage element is implemented as a ternary SRAM cell. This paper also presents the first verification of read/write schemes that consider noise margins.
UR - http://www.scopus.com/inward/record.url?scp=85109030863&partnerID=8YFLogxK
U2 - 10.1109/ISCAS51556.2021.9401259
DO - 10.1109/ISCAS51556.2021.9401259
M3 - Conference contribution
AN - SCOPUS:85109030863
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021
Y2 - 22 May 2021 through 28 May 2021
ER -