Design and analysis of Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET)

Jae Hwa Seo; Young Jun Yoon; Seongmin Lee; Jung Hee Lee; Seongjae Cho; In Man Kang

doi:10.1016/j.cap.2014.12.013

Design and analysis of Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET)

Jae Hwa Seo, Young Jun Yoon, Seongmin Lee, Jung Hee Lee, Seongjae Cho, In Man Kang

School of Electronics Engineering

Research output: Contribution to journal › Article › peer-review

33 Scopus citations

Abstract

In this work, a Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET) has been designed and analyzed. Various studies on III-V compound semiconductor materials for applications in TFET devices have been made and we adopt one of them to perform a physical design for boosting the tunneling probability. The GAA structure has a partially open region for extending the tunneling area and the channel is under the GAA region, which makes it an arch-shaped GAA structure. We have performed the design optimization with variables of epitaxy channel thickness (t_epi) and height of source region (H_source) in the Si-based TFET. The designed arch-shaped GAA TFET based on Si platform demonstrates excellent performances for low-power (LP) applications including on-state current (I_on) of 694 μA/μm, subthreshold swing (S) of 7.8 mV/dec, threshold voltage (V_t) of 0.1 V, current gain cut-off frequency (f_T) of 12 GHz, and maximum oscillation frequency (f_max) of 283 GHz.

Original language	English
Pages (from-to)	208-212
Number of pages	5
Journal	Current Applied Physics
Volume	15
Issue number	3
DOIs	https://doi.org/10.1016/j.cap.2014.12.013
State	Published - Mar 2015

Keywords

Design optimization
Gate-all-around (GAA)
Low-power (LP)
Physical design
Tunneling field-effect transistor (TFET)

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10.1016/j.cap.2014.12.013

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title = "Design and analysis of Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET)",

abstract = "In this work, a Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET) has been designed and analyzed. Various studies on III-V compound semiconductor materials for applications in TFET devices have been made and we adopt one of them to perform a physical design for boosting the tunneling probability. The GAA structure has a partially open region for extending the tunneling area and the channel is under the GAA region, which makes it an arch-shaped GAA structure. We have performed the design optimization with variables of epitaxy channel thickness (tepi) and height of source region (Hsource) in the Si-based TFET. The designed arch-shaped GAA TFET based on Si platform demonstrates excellent performances for low-power (LP) applications including on-state current (Ion) of 694 μA/μm, subthreshold swing (S) of 7.8 mV/dec, threshold voltage (Vt) of 0.1 V, current gain cut-off frequency (fT) of 12 GHz, and maximum oscillation frequency (fmax) of 283 GHz.",

keywords = "Design optimization, Gate-all-around (GAA), Low-power (LP), Physical design, Tunneling field-effect transistor (TFET)",

author = "Seo, \{Jae Hwa\} and Yoon, \{Young Jun\} and Seongmin Lee and Lee, \{Jung Hee\} and Seongjae Cho and Kang, \{In Man\}",

year = "2015",

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doi = "10.1016/j.cap.2014.12.013",

language = "English",

volume = "15",

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T1 - Design and analysis of Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET)

AU - Seo, Jae Hwa

AU - Yoon, Young Jun

AU - Lee, Seongmin

AU - Lee, Jung Hee

AU - Cho, Seongjae

AU - Kang, In Man

PY - 2015/3

Y1 - 2015/3

N2 - In this work, a Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET) has been designed and analyzed. Various studies on III-V compound semiconductor materials for applications in TFET devices have been made and we adopt one of them to perform a physical design for boosting the tunneling probability. The GAA structure has a partially open region for extending the tunneling area and the channel is under the GAA region, which makes it an arch-shaped GAA structure. We have performed the design optimization with variables of epitaxy channel thickness (tepi) and height of source region (Hsource) in the Si-based TFET. The designed arch-shaped GAA TFET based on Si platform demonstrates excellent performances for low-power (LP) applications including on-state current (Ion) of 694 μA/μm, subthreshold swing (S) of 7.8 mV/dec, threshold voltage (Vt) of 0.1 V, current gain cut-off frequency (fT) of 12 GHz, and maximum oscillation frequency (fmax) of 283 GHz.

AB - In this work, a Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET) has been designed and analyzed. Various studies on III-V compound semiconductor materials for applications in TFET devices have been made and we adopt one of them to perform a physical design for boosting the tunneling probability. The GAA structure has a partially open region for extending the tunneling area and the channel is under the GAA region, which makes it an arch-shaped GAA structure. We have performed the design optimization with variables of epitaxy channel thickness (tepi) and height of source region (Hsource) in the Si-based TFET. The designed arch-shaped GAA TFET based on Si platform demonstrates excellent performances for low-power (LP) applications including on-state current (Ion) of 694 μA/μm, subthreshold swing (S) of 7.8 mV/dec, threshold voltage (Vt) of 0.1 V, current gain cut-off frequency (fT) of 12 GHz, and maximum oscillation frequency (fmax) of 283 GHz.

KW - Design optimization

KW - Gate-all-around (GAA)

KW - Low-power (LP)

KW - Physical design

KW - Tunneling field-effect transistor (TFET)

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DO - 10.1016/j.cap.2014.12.013

M3 - Article

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SN - 1567-1739

VL - 15

SP - 208

EP - 212

JO - Current Applied Physics

JF - Current Applied Physics

IS - 3

ER -

Design and analysis of Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET)

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Keywords

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