Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor

Dongyun Kam; Jung Gyu Min; Jongho Yoon; Sunmean Kim; Seokhyeong Kang; Youngjoo Lee

doi:10.23919/DATE54114.2022.9774584

Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor

Dongyun Kam, Jung Gyu Min, Jongho Yoon, Sunmean Kim, Seokhyeong Kang, Youngjoo Lee

School of Electronics Engineering

Pohang University of Science and Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

In this paper, we introduce the design and veri-fication frameworks for developing a fully-functional emerging ternary processor. Based on the existing compiling environments for binary processors, for the given ternary instructions, the software-level framework provides an efficient way to convert the given programs to the ternary assembly codes. We also present a hardware-level framework to rapidly evaluate the performance of a ternary processor implemented in arbitrary design technology. As a case study, the fully-functional 9-trit advanced RISC-based ternary (ART-9) core is newly developed by using the proposed frameworks. Utilizing 24 custom ternary instructions, the 5-stage ART-9 prototype architecture is successfully verified by a number of test programs including dhrystone benchmark in a ternary domain, achieving the processing efficiency of 57.8 DMIPS/W and 3.06times 10^{6} DMIPS/W in the FPGA-level ternary-logic emulations and the emerging CNTFET ternary gates, respectively.

Original language	English
Title of host publication	Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022
Editors	Cristiana Bolchini, Ingrid Verbauwhede, Ioana Vatajelu
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1077-1082
Number of pages	6
ISBN (Electronic)	9783981926361
DOIs	https://doi.org/10.23919/DATE54114.2022.9774584
State	Published - 2022
Event	2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022 - Virtual, Online, Belgium Duration: 14 Mar 2022 → 23 Mar 2022

Publication series

Name	Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022

Conference

Conference	2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022
Country/Territory	Belgium
City	Virtual, Online
Period	14/03/22 → 23/03/22

Keywords

Emerging computer design
Instruction set architecture
Multi-valued logic circuits
RISC
Ternary processor

Access to Document

10.23919/DATE54114.2022.9774584

Cite this

Kam, D., Min, J. G., Yoon, J., Kim, S., Kang, S., & Lee, Y. (2022). Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor. In C. Bolchini, I. Verbauwhede, & I. Vatajelu (Eds.), Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022 (pp. 1077-1082). (Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/DATE54114.2022.9774584

Kam, Dongyun ; Min, Jung Gyu ; Yoon, Jongho et al. / Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor. Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022. editor / Cristiana Bolchini ; Ingrid Verbauwhede ; Ioana Vatajelu. Institute of Electrical and Electronics Engineers Inc., 2022. pp. 1077-1082 (Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022).

@inproceedings{8b4bdfa0158f42a0b3fe95cd59d16bef,

title = "Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor",

abstract = "In this paper, we introduce the design and veri-fication frameworks for developing a fully-functional emerging ternary processor. Based on the existing compiling environments for binary processors, for the given ternary instructions, the software-level framework provides an efficient way to convert the given programs to the ternary assembly codes. We also present a hardware-level framework to rapidly evaluate the performance of a ternary processor implemented in arbitrary design technology. As a case study, the fully-functional 9-trit advanced RISC-based ternary (ART-9) core is newly developed by using the proposed frameworks. Utilizing 24 custom ternary instructions, the 5-stage ART-9 prototype architecture is successfully verified by a number of test programs including dhrystone benchmark in a ternary domain, achieving the processing efficiency of 57.8 DMIPS/W and 3.06times 10^{6} DMIPS/W in the FPGA-level ternary-logic emulations and the emerging CNTFET ternary gates, respectively.",

keywords = "Emerging computer design, Instruction set architecture, Multi-valued logic circuits, RISC, Ternary processor",

author = "Dongyun Kam and Min, {Jung Gyu} and Jongho Yoon and Sunmean Kim and Seokhyeong Kang and Youngjoo Lee",

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year = "2022",

doi = "10.23919/DATE54114.2022.9774584",

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Kam, D, Min, JG, Yoon, J, Kim, S, Kang, S & Lee, Y 2022, Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor. in C Bolchini, I Verbauwhede & I Vatajelu (eds), Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022. Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022, Institute of Electrical and Electronics Engineers Inc., pp. 1077-1082, 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022, Virtual, Online, Belgium, 14/03/22. https://doi.org/10.23919/DATE54114.2022.9774584

Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor. / Kam, Dongyun; Min, Jung Gyu; Yoon, Jongho et al.
Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022. ed. / Cristiana Bolchini; Ingrid Verbauwhede; Ioana Vatajelu. Institute of Electrical and Electronics Engineers Inc., 2022. p. 1077-1082 (Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor

AU - Kam, Dongyun

AU - Min, Jung Gyu

AU - Yoon, Jongho

AU - Kim, Sunmean

AU - Kang, Seokhyeong

AU - Lee, Youngjoo

PY - 2022

Y1 - 2022

N2 - In this paper, we introduce the design and veri-fication frameworks for developing a fully-functional emerging ternary processor. Based on the existing compiling environments for binary processors, for the given ternary instructions, the software-level framework provides an efficient way to convert the given programs to the ternary assembly codes. We also present a hardware-level framework to rapidly evaluate the performance of a ternary processor implemented in arbitrary design technology. As a case study, the fully-functional 9-trit advanced RISC-based ternary (ART-9) core is newly developed by using the proposed frameworks. Utilizing 24 custom ternary instructions, the 5-stage ART-9 prototype architecture is successfully verified by a number of test programs including dhrystone benchmark in a ternary domain, achieving the processing efficiency of 57.8 DMIPS/W and 3.06times 10^{6} DMIPS/W in the FPGA-level ternary-logic emulations and the emerging CNTFET ternary gates, respectively.

AB - In this paper, we introduce the design and veri-fication frameworks for developing a fully-functional emerging ternary processor. Based on the existing compiling environments for binary processors, for the given ternary instructions, the software-level framework provides an efficient way to convert the given programs to the ternary assembly codes. We also present a hardware-level framework to rapidly evaluate the performance of a ternary processor implemented in arbitrary design technology. As a case study, the fully-functional 9-trit advanced RISC-based ternary (ART-9) core is newly developed by using the proposed frameworks. Utilizing 24 custom ternary instructions, the 5-stage ART-9 prototype architecture is successfully verified by a number of test programs including dhrystone benchmark in a ternary domain, achieving the processing efficiency of 57.8 DMIPS/W and 3.06times 10^{6} DMIPS/W in the FPGA-level ternary-logic emulations and the emerging CNTFET ternary gates, respectively.

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BT - Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022

A2 - Bolchini, Cristiana

A2 - Verbauwhede, Ingrid

A2 - Vatajelu, Ioana

PB - Institute of Electrical and Electronics Engineers Inc.

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Y2 - 14 March 2022 through 23 March 2022

ER -

Kam D, Min JG, Yoon J, Kim S, Kang S, Lee Y. Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor. In Bolchini C, Verbauwhede I, Vatajelu I, editors, Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022. Institute of Electrical and Electronics Engineers Inc. 2022. p. 1077-1082. (Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022). doi: 10.23919/DATE54114.2022.9774584

Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor

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