Design of 256-Kb low-power embedded SRAM

This work presents a low voltage SRAM design technique to increase the operating margin. For each read/write cycle, the wordline and cell power node of selected SRAM cells are boosted into two different voltage levels. This technique enhances the read static noise margin (SNM) to a sufficient amount without an increase of cell size. It also improves the SRAM circuit speed owing to an increase of the cell read-out current. A 0.18-μm CMOS 256-Kbit SRAM macro has been fabricated with the proposed technique. The chip operates with 50 MHz at 0.8 V supply voltage. It consumes a power of 65 μW/MHz. Measurement shows that the proposed SRAM configuration achieves a reduction by 87 % in bit-error rate while operating with 43 % higher clock frequency compared with that of conventional SRAM.