Design of a gate-all-around arch-shaped tunnel-field-effect-transistor-based capacitorless DRAM

Engineering

• Arch 100%
• Tunnel field effect transistors 100%
• Heterojunctions 66%
• Tunnel Construction 66%
• Simulation Result 33%
• Dynamic Random Access Memory 33%
• Retention Time 33%
• Current Ratio 33%
• Memory Performance 33%
• Quantum Well 33%
• Charge Carrier 33%
• Electric Field 33%
• Transistor 33%

Material Science

• Density 100%
• Heterojunction 100%
• Field Effect Transistor 100%
• Transistor 50%
• Charge Carrier 50%
• Quantum Well 50%
• Germanium 50%

Computer Science

• Effect Transistor 100%
• Application Memory 100%
• Energy Consumption 50%
• Read Operation 50%
• Superior Performance 50%
• Dynamic Random Access Memory 50%
• Memory Performance 50%
• Transistor 50%