Design of a Low-Cost Approximate Adder with a Zero Truncation

Jungwon Lee; Hyoju Seo; Yerin Kim; Yongtae Kim

doi:10.1109/ISOCC50952.2020.9332971

Design of a Low-Cost Approximate Adder with a Zero Truncation

Jungwon Lee, Hyoju Seo, Yerin Kim, Yongtae Kim

Kyungpook National University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

8 Scopus citations

Abstract

We propose a cost-effective approximate adder using a zero truncation technique with acceptable accuracy. The proposed adder design reduces the area by up to 23% compared to the approximate adders considered in this paper when implemented with a 32-nm CMOS technology. Furthermore, our adder shows 16%, 10%, 10%, and 16% better performance in area, power, power-delay product, and area-delay product, respectively, than the lower-part OR adder while providing an acceptable accuracy performance. To see the impact of approximation errors caused by our adder on real applications, it is adopted in a digital image processing and demonstrates that our adder rarely affects the output image quality.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference, ISOCC 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	69-70
Number of pages	2
ISBN (Electronic)	9781728183312
DOIs	https://doi.org/10.1109/ISOCC50952.2020.9332971
State	Published - 21 Oct 2020
Event	17th International System-on-Chip Design Conference, ISOCC 2020 - Yeosu, Korea, Republic of Duration: 21 Oct 2020 → 24 Oct 2020

Publication series

Name	Proceedings - International SoC Design Conference, ISOCC 2020

Conference

Conference	17th International System-on-Chip Design Conference, ISOCC 2020
Country/Territory	Korea, Republic of
City	Yeosu
Period	21/10/20 → 24/10/20

Keywords

approximate adder
approximate computing
energy efficiency
low power
zero truncation

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/ISOCC50952.2020.9332971

Cite this

Lee, J., Seo, H., Kim, Y., & Kim, Y. (2020). Design of a Low-Cost Approximate Adder with a Zero Truncation. In Proceedings - International SoC Design Conference, ISOCC 2020 (pp. 69-70). Article 9332971 (Proceedings - International SoC Design Conference, ISOCC 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC50952.2020.9332971

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abstract = "We propose a cost-effective approximate adder using a zero truncation technique with acceptable accuracy. The proposed adder design reduces the area by up to 23% compared to the approximate adders considered in this paper when implemented with a 32-nm CMOS technology. Furthermore, our adder shows 16%, 10%, 10%, and 16% better performance in area, power, power-delay product, and area-delay product, respectively, than the lower-part OR adder while providing an acceptable accuracy performance. To see the impact of approximation errors caused by our adder on real applications, it is adopted in a digital image processing and demonstrates that our adder rarely affects the output image quality.",

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author = "Jungwon Lee and Hyoju Seo and Yerin Kim and Yongtae Kim",

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year = "2020",

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doi = "10.1109/ISOCC50952.2020.9332971",

language = "English",

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Lee, J, Seo, H, Kim, Y & Kim, Y 2020, Design of a Low-Cost Approximate Adder with a Zero Truncation. in Proceedings - International SoC Design Conference, ISOCC 2020., 9332971, Proceedings - International SoC Design Conference, ISOCC 2020, Institute of Electrical and Electronics Engineers Inc., pp. 69-70, 17th International System-on-Chip Design Conference, ISOCC 2020, Yeosu, Korea, Republic of, 21/10/20. https://doi.org/10.1109/ISOCC50952.2020.9332971

Design of a Low-Cost Approximate Adder with a Zero Truncation. / Lee, Jungwon; Seo, Hyoju; Kim, Yerin et al.
Proceedings - International SoC Design Conference, ISOCC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 69-70 9332971 (Proceedings - International SoC Design Conference, ISOCC 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - We propose a cost-effective approximate adder using a zero truncation technique with acceptable accuracy. The proposed adder design reduces the area by up to 23% compared to the approximate adders considered in this paper when implemented with a 32-nm CMOS technology. Furthermore, our adder shows 16%, 10%, 10%, and 16% better performance in area, power, power-delay product, and area-delay product, respectively, than the lower-part OR adder while providing an acceptable accuracy performance. To see the impact of approximation errors caused by our adder on real applications, it is adopted in a digital image processing and demonstrates that our adder rarely affects the output image quality.

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Design of a Low-Cost Approximate Adder with a Zero Truncation

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Keywords

UN SDGs

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