TY - GEN
T1 - Design of a Low-Cost Stochastic Computing-based Median Filter for Digital Image Processing
AU - Lee, Donghui
AU - Kim, Yongtae
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - Stochastic computing (SC) is an approximate computation method that enables the design of low-cost and error-tolerant systems. The median filter (MF) is one of the widely used filters in image processing and is particularly effective in removing salt-and-pepper noise. In this paper, we propose an energy-efficient SC-based MF. The proposed SC-based MF increases hardware efficiency while maintaining performance quality by reducing the number of comparators. The proposed SC-based MF was implemented using Verilog HDL and synthesized using 65-nm CMOS technology. The proposed SC-based MF achieves up to 63.4% and 75.2% savings in area and power, respectively, compared to the binary implementation of MF. Furthermore, compared to the conventional SC-based MF, the proposed design improves by 13.2% and 10.2%, respectively. Despite a slight decrease in peak signal-to-noise ratio (PSNR), the proposed design exhibits excellent overall hardware performance.
AB - Stochastic computing (SC) is an approximate computation method that enables the design of low-cost and error-tolerant systems. The median filter (MF) is one of the widely used filters in image processing and is particularly effective in removing salt-and-pepper noise. In this paper, we propose an energy-efficient SC-based MF. The proposed SC-based MF increases hardware efficiency while maintaining performance quality by reducing the number of comparators. The proposed SC-based MF was implemented using Verilog HDL and synthesized using 65-nm CMOS technology. The proposed SC-based MF achieves up to 63.4% and 75.2% savings in area and power, respectively, compared to the binary implementation of MF. Furthermore, compared to the conventional SC-based MF, the proposed design improves by 13.2% and 10.2%, respectively. Despite a slight decrease in peak signal-to-noise ratio (PSNR), the proposed design exhibits excellent overall hardware performance.
KW - comparator
KW - median filter
KW - stochastic computing
UR - http://www.scopus.com/inward/record.url?scp=85213337698&partnerID=8YFLogxK
U2 - 10.1109/ISOCC62682.2024.10762709
DO - 10.1109/ISOCC62682.2024.10762709
M3 - Conference contribution
AN - SCOPUS:85213337698
T3 - Proceedings - International SoC Design Conference 2024, ISOCC 2024
SP - 298
EP - 299
BT - Proceedings - International SoC Design Conference 2024, ISOCC 2024
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 21st International System-on-Chip Design Conference, ISOCC 2024
Y2 - 19 August 2024 through 22 August 2024
ER -