Design of advanced subthreshold SRAM array for ultra-low power technology

With scaling of CMOS technology, data stability of SRAM at ultra-low supply voltage has become a critical issue for wearable system applications. In this paper, we present an advanced 8T SRAM which can operate properly in subthreshold voltage regime. The bit-cell utilizes a differential swing in the read and write path, and allows an efficient column-interleaving structure. In the read operation, a column-wise assistline scheme of the cell leads to the cell being unaffected by the read disturbance. In addition, the bit-cell keeps the noise-vulnerable data 'low' node voltage close to the ground level during the dummy-read operation, thus producing near-ideal voltage transfer characteristics essential for robust SRAM functionality. In the write access, the boosted wordline facilitates to change the contents of the memory bit. Implementation results with 180 nm CMOS technology exhibit that the proposed SRAM remains unaffected by the read disturbance, while achieves 59.8 % higher dummy-read stability and 3.7 times better write-ability at a subthreshold supply voltage compared to the conventional 6T SRAM.