Design of an Accuracy Enhanced Imprecise Adder with Half Adder-based Approximation

Hyoju Seo; Jungwon Lee; Hyelin Seok; Yongtae Kim

doi:10.1109/ISOCC53507.2021.9613888

Design of an Accuracy Enhanced Imprecise Adder with Half Adder-based Approximation

Hyoju Seo
, Jungwon Lee
, Hyelin Seok
, Yongtae Kim

Kyungpook National University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

This paper proposes a new approximate adder that increases the accuracy of addition while ensuring acceptable hardware performance. The proposed adder implemented with a 32-nm CMOS technology reduces the area, power, and delay by 40%, 43%, and 50% of those of the traditional accurate adder, respectively. Moreover, the proposed adder shows a better tradeoff performance than the existing approximate adders considered in this paper when jointly evaluating both accuracy and hardware performance. Specifically, the proposed adder enhances power-mean relative error distance (MRED) product, energy-MRED product, and area-MRED product by up to 65%, 65%, and 64% compared to the approximate adder considered herein.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2021, ISOCC 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	153-154
Number of pages	2
ISBN (Electronic)	9781665401746
DOIs	https://doi.org/10.1109/ISOCC53507.2021.9613888
State	Published - 2021
Event	18th International System-on-Chip Design Conference, ISOCC 2021 - Jeju Island, Korea, Republic of Duration: 6 Oct 2021 → 9 Oct 2021

Publication series

Name	Proceedings - International SoC Design Conference 2021, ISOCC 2021

Conference

Conference	18th International System-on-Chip Design Conference, ISOCC 2021
Country/Territory	Korea, Republic of
City	Jeju Island
Period	6/10/21 → 9/10/21

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

approximate adder
approximate computing
energy efficiency
low power

Access to Document

10.1109/ISOCC53507.2021.9613888

Cite this

Seo, H., Lee, J., Seok, H., & Kim, Y. (2021). Design of an Accuracy Enhanced Imprecise Adder with Half Adder-based Approximation. In Proceedings - International SoC Design Conference 2021, ISOCC 2021 (pp. 153-154). (Proceedings - International SoC Design Conference 2021, ISOCC 2021). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC53507.2021.9613888

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title = "Design of an Accuracy Enhanced Imprecise Adder with Half Adder-based Approximation",

abstract = "This paper proposes a new approximate adder that increases the accuracy of addition while ensuring acceptable hardware performance. The proposed adder implemented with a 32-nm CMOS technology reduces the area, power, and delay by 40\%, 43\%, and 50\% of those of the traditional accurate adder, respectively. Moreover, the proposed adder shows a better tradeoff performance than the existing approximate adders considered in this paper when jointly evaluating both accuracy and hardware performance. Specifically, the proposed adder enhances power-mean relative error distance (MRED) product, energy-MRED product, and area-MRED product by up to 65\%, 65\%, and 64\% compared to the approximate adder considered herein.",

keywords = "approximate adder, approximate computing, energy efficiency, low power",

author = "Hyoju Seo and Jungwon Lee and Hyelin Seok and Yongtae Kim",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 18th International System-on-Chip Design Conference, ISOCC 2021 ; Conference date: 06-10-2021 Through 09-10-2021",

year = "2021",

doi = "10.1109/ISOCC53507.2021.9613888",

language = "English",

series = "Proceedings - International SoC Design Conference 2021, ISOCC 2021",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "153--154",

booktitle = "Proceedings - International SoC Design Conference 2021, ISOCC 2021",

address = "United States",

}

Seo, H, Lee, J, Seok, H & Kim, Y 2021, Design of an Accuracy Enhanced Imprecise Adder with Half Adder-based Approximation. in Proceedings - International SoC Design Conference 2021, ISOCC 2021. Proceedings - International SoC Design Conference 2021, ISOCC 2021, Institute of Electrical and Electronics Engineers Inc., pp. 153-154, 18th International System-on-Chip Design Conference, ISOCC 2021, Jeju Island, Korea, Republic of, 6/10/21. https://doi.org/10.1109/ISOCC53507.2021.9613888

Design of an Accuracy Enhanced Imprecise Adder with Half Adder-based Approximation. / Seo, Hyoju; Lee, Jungwon; Seok, Hyelin et al.
Proceedings - International SoC Design Conference 2021, ISOCC 2021. Institute of Electrical and Electronics Engineers Inc., 2021. p. 153-154 (Proceedings - International SoC Design Conference 2021, ISOCC 2021).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Design of an Accuracy Enhanced Imprecise Adder with Half Adder-based Approximation

AU - Seo, Hyoju

AU - Lee, Jungwon

AU - Seok, Hyelin

AU - Kim, Yongtae

PY - 2021

Y1 - 2021

N2 - This paper proposes a new approximate adder that increases the accuracy of addition while ensuring acceptable hardware performance. The proposed adder implemented with a 32-nm CMOS technology reduces the area, power, and delay by 40%, 43%, and 50% of those of the traditional accurate adder, respectively. Moreover, the proposed adder shows a better tradeoff performance than the existing approximate adders considered in this paper when jointly evaluating both accuracy and hardware performance. Specifically, the proposed adder enhances power-mean relative error distance (MRED) product, energy-MRED product, and area-MRED product by up to 65%, 65%, and 64% compared to the approximate adder considered herein.

AB - This paper proposes a new approximate adder that increases the accuracy of addition while ensuring acceptable hardware performance. The proposed adder implemented with a 32-nm CMOS technology reduces the area, power, and delay by 40%, 43%, and 50% of those of the traditional accurate adder, respectively. Moreover, the proposed adder shows a better tradeoff performance than the existing approximate adders considered in this paper when jointly evaluating both accuracy and hardware performance. Specifically, the proposed adder enhances power-mean relative error distance (MRED) product, energy-MRED product, and area-MRED product by up to 65%, 65%, and 64% compared to the approximate adder considered herein.

KW - approximate adder

KW - approximate computing

KW - energy efficiency

KW - low power

UR - https://www.scopus.com/pages/publications/85123382615

U2 - 10.1109/ISOCC53507.2021.9613888

DO - 10.1109/ISOCC53507.2021.9613888

M3 - Conference contribution

AN - SCOPUS:85123382615

T3 - Proceedings - International SoC Design Conference 2021, ISOCC 2021

SP - 153

EP - 154

BT - Proceedings - International SoC Design Conference 2021, ISOCC 2021

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 18th International System-on-Chip Design Conference, ISOCC 2021

Y2 - 6 October 2021 through 9 October 2021

ER -

Design of an Accuracy Enhanced Imprecise Adder with Half Adder-based Approximation

Abstract

Publication series

Conference

UN SDGs

Keywords

Access to Document

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