@inproceedings{efa7d9b070c24d839394e62826ba5685,
title = "Design of logic-compatible embedded DRAM using gain memory cell",
abstract = "In this work, we present an embedded DRAM utilizing logic-compatible 2T gain cell. The memory cells are composed of a high-VTH write NMOS and a standard read NMOS. Due to the combination of low off-leakage write device and high mobility read device, this NMOS-based hybrid gain cell provides much improved data retention and read performance. At 1.2 V and 85 °C, the proposed bit-cell achieves 1.1× longer standby retention and 4.4× longer write disturbance retention compared to the PMOS-only 2T cell. The memory arrays operate with a logic-compatible supply voltage; /CS controlled 128-row refresh; and nondestructive read with speed comparable to 6T SRAM but 65 % smaller cell area. Design results from a test chip in a 130 nm logic CMOS technology exhibit the effectiveness of the proposed embedded memory techniques.",
keywords = "data retention, embedded DRAM, gain cell memory",
author = "Weijie Cheng and Cho, {Jeong Wook} and Yeonbae Chung",
year = "2012",
doi = "10.1109/ISOCC.2012.6407073",
language = "English",
isbn = "9781467329880",
series = "ISOCC 2012 - 2012 International SoC Design Conference",
pages = "196--199",
booktitle = "ISOCC 2012 - 2012 International SoC Design Conference",
note = "2012 International SoC Design Conference, ISOCC 2012 ; Conference date: 04-11-2012 Through 07-11-2012",
}