@inproceedings{a4df765c686a4a0f8f11cf41f93a5ed8,
title = "Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic",
abstract = "We propose a quad-edge-triggered flip-flop which captures and propagates a ternary data signal at four-edges of a ternary clock signal. The proposed circuit uses carbon nanotube FETs and consists of four types of logic gate: ternary clock driver, standard ternary inverter, binary inverter, and transmission gate. HSPICE simulation result has confirmed that power consumption of QETFF is lower than conventional single-edge-triggered flip-flop. The average power consumption is reduced by 31 % in flip-flop and 75 % in clock tree. We designed a ternary serial adder using QETFF and the energy efficiency of the proposed circuit is significantly improved compared to the previous design of ternary serial adder.",
keywords = "CNTFET, Multi-valued logic, Sequen-tiallogic circuits, Ternary clock signal, Ternary logic circuits",
author = "Sunmean Kim and Lee, {Sung Yun} and Sunghye Park and Seokhyeong Kang",
note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 49th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2019 ; Conference date: 21-05-2019 Through 23-05-2019",
year = "2019",
month = may,
doi = "10.1109/ISMVL.2019.00015",
language = "English",
series = "Proceedings of The International Symposium on Multiple-Valued Logic",
publisher = "IEEE Computer Society",
pages = "37--42",
booktitle = "Proceedings - 2019 IEEE 49th International Symposium on Multiple-Valued Logic, ISMVL 2019",
address = "United States",
}
