Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic

Sunmean Kim; Sung Yun Lee; Sunghye Park; Seokhyeong Kang

doi:10.1109/ISMVL.2019.00015

Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic

Sunmean Kim
, Sung Yun Lee
, Sunghye Park
, Seokhyeong Kang

School of Electronics Engineering

Pohang University of Science and Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

11 Scopus citations

Abstract

We propose a quad-edge-triggered flip-flop which captures and propagates a ternary data signal at four-edges of a ternary clock signal. The proposed ci^rcuit uses carbon nanotube FETs and consists of four types of logic gate: ternary clock driver, standard ternary inverter, binary inverter, and transmission gate. HSPICE simulation result has confirmed that power consumption of QETFF is lower than conventional single-edge-triggered flip-flop. The average power consumption is reduced by 31 % in flip-flop and 75 % in clock tree. We designed a ternary serial adder using QETFF and the energy efficiency of the proposed circuit is significantly improved compared to the previous design of ternary serial adder.

Original language	English
Title of host publication	Proceedings - 2019 IEEE 49th International Symposium on Multiple-Valued Logic, ISMVL 2019
Publisher	IEEE Computer Society
Pages	37-42
Number of pages	6
ISBN (Electronic)	9781728100913
DOIs	https://doi.org/10.1109/ISMVL.2019.00015
State	Published - May 2019
Event	49th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2019 - Fredericton, Canada Duration: 21 May 2019 → 23 May 2019

Publication series

Name	Proceedings of The International Symposium on Multiple-Valued Logic
Volume	2019-May
ISSN (Print)	0195-623X

Conference

Conference	49th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2019
Country/Territory	Canada
City	Fredericton
Period	21/05/19 → 23/05/19

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

CNTFET
Multi-valued logic
Sequen-tiallogic circuits
Ternary clock signal
Ternary logic circuits

Access to Document

10.1109/ISMVL.2019.00015

Cite this

Kim, S., Lee, S. Y., Park, S., & Kang, S. (2019). Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic. In Proceedings - 2019 IEEE 49th International Symposium on Multiple-Valued Logic, ISMVL 2019 (pp. 37-42). Article 8758742 (Proceedings of The International Symposium on Multiple-Valued Logic; Vol. 2019-May). IEEE Computer Society. https://doi.org/10.1109/ISMVL.2019.00015

@inproceedings{a4df765c686a4a0f8f11cf41f93a5ed8,

title = "Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic",

abstract = "We propose a quad-edge-triggered flip-flop which captures and propagates a ternary data signal at four-edges of a ternary clock signal. The proposed circuit uses carbon nanotube FETs and consists of four types of logic gate: ternary clock driver, standard ternary inverter, binary inverter, and transmission gate. HSPICE simulation result has confirmed that power consumption of QETFF is lower than conventional single-edge-triggered flip-flop. The average power consumption is reduced by 31 \% in flip-flop and 75 \% in clock tree. We designed a ternary serial adder using QETFF and the energy efficiency of the proposed circuit is significantly improved compared to the previous design of ternary serial adder.",

keywords = "CNTFET, Multi-valued logic, Sequen-tiallogic circuits, Ternary clock signal, Ternary logic circuits",

author = "Sunmean Kim and Lee, \{Sung Yun\} and Sunghye Park and Seokhyeong Kang",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 49th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2019 ; Conference date: 21-05-2019 Through 23-05-2019",

year = "2019",

month = may,

doi = "10.1109/ISMVL.2019.00015",

language = "English",

series = "Proceedings of The International Symposium on Multiple-Valued Logic",

publisher = "IEEE Computer Society",

pages = "37--42",

booktitle = "Proceedings - 2019 IEEE 49th International Symposium on Multiple-Valued Logic, ISMVL 2019",

address = "United States",

}

Kim, S, Lee, SY, Park, S & Kang, S 2019, Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic. in Proceedings - 2019 IEEE 49th International Symposium on Multiple-Valued Logic, ISMVL 2019., 8758742, Proceedings of The International Symposium on Multiple-Valued Logic, vol. 2019-May, IEEE Computer Society, pp. 37-42, 49th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2019, Fredericton, Canada, 21/05/19. https://doi.org/10.1109/ISMVL.2019.00015

Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic. / Kim, Sunmean; Lee, Sung Yun; Park, Sunghye et al.
Proceedings - 2019 IEEE 49th International Symposium on Multiple-Valued Logic, ISMVL 2019. IEEE Computer Society, 2019. p. 37-42 8758742 (Proceedings of The International Symposium on Multiple-Valued Logic; Vol. 2019-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic

AU - Kim, Sunmean

AU - Lee, Sung Yun

AU - Park, Sunghye

AU - Kang, Seokhyeong

PY - 2019/5

Y1 - 2019/5

N2 - We propose a quad-edge-triggered flip-flop which captures and propagates a ternary data signal at four-edges of a ternary clock signal. The proposed circuit uses carbon nanotube FETs and consists of four types of logic gate: ternary clock driver, standard ternary inverter, binary inverter, and transmission gate. HSPICE simulation result has confirmed that power consumption of QETFF is lower than conventional single-edge-triggered flip-flop. The average power consumption is reduced by 31 % in flip-flop and 75 % in clock tree. We designed a ternary serial adder using QETFF and the energy efficiency of the proposed circuit is significantly improved compared to the previous design of ternary serial adder.

AB - We propose a quad-edge-triggered flip-flop which captures and propagates a ternary data signal at four-edges of a ternary clock signal. The proposed circuit uses carbon nanotube FETs and consists of four types of logic gate: ternary clock driver, standard ternary inverter, binary inverter, and transmission gate. HSPICE simulation result has confirmed that power consumption of QETFF is lower than conventional single-edge-triggered flip-flop. The average power consumption is reduced by 31 % in flip-flop and 75 % in clock tree. We designed a ternary serial adder using QETFF and the energy efficiency of the proposed circuit is significantly improved compared to the previous design of ternary serial adder.

KW - CNTFET

KW - Multi-valued logic

KW - Sequen-tiallogic circuits

KW - Ternary clock signal

KW - Ternary logic circuits

UR - https://www.scopus.com/pages/publications/85069155462

U2 - 10.1109/ISMVL.2019.00015

DO - 10.1109/ISMVL.2019.00015

M3 - Conference contribution

AN - SCOPUS:85069155462

T3 - Proceedings of The International Symposium on Multiple-Valued Logic

SP - 37

EP - 42

BT - Proceedings - 2019 IEEE 49th International Symposium on Multiple-Valued Logic, ISMVL 2019

PB - IEEE Computer Society

T2 - 49th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2019

Y2 - 21 May 2019 through 23 May 2019

ER -

Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic

Abstract

Publication series

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UN SDGs

Keywords

Access to Document

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