TY - GEN
T1 - Design of the clock recovery circuit with a phase-locked loop for 40 Gb/s optical receivers
AU - Park, Chan Ho
AU - Woo, Dong Sik
AU - Kim, Kang Wook
AU - Lim, Sang Kyu
PY - 2004
Y1 - 2004
N2 - A clock recovery circuit for a 40 Gb/s optical receiver has been designed and implemented. The clock recovery circuit consists of a pre-amplifier, a nonlinear circuit with diodes, a bandpass filter and a clock amplifier. When a 40 Gb/s signal of 0 dBm was applied to the input of the circuit, the 40 GHz clock was recovered with the -2 dBm output power. The implemented clock recovery circuit is to be used for the input of a phase-locked loop to further stabilize the recovered clock signal and to reduce the clock jitter. Clock recovery circuit, 40 Gb/s, Optical receiver.
AB - A clock recovery circuit for a 40 Gb/s optical receiver has been designed and implemented. The clock recovery circuit consists of a pre-amplifier, a nonlinear circuit with diodes, a bandpass filter and a clock amplifier. When a 40 Gb/s signal of 0 dBm was applied to the input of the circuit, the 40 GHz clock was recovered with the -2 dBm output power. The implemented clock recovery circuit is to be used for the input of a phase-locked loop to further stabilize the recovered clock signal and to reduce the clock jitter. Clock recovery circuit, 40 Gb/s, Optical receiver.
UR - http://www.scopus.com/inward/record.url?scp=18744369382&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:18744369382
SN - 1580539920
SN - 9781580539920
T3 - Conference Proceedings- European Microwave Conference
SP - 757
EP - 759
BT - Conference Proceedings- 34th European Microwave Conference
T2 - Conference Proceedings- 34th European Microwave Conference
Y2 - 12 October 2004 through 14 October 2004
ER -