Design optimization and analysis of InGaAs-based gate-all-around (GAA) junctionless field-effect transistor (JLFET)

In this study, the InGaAs-based gate-all-around (GAA) JLFET is designed and analyzed with three-dimensional (3D) technology computer-aided design (TCAD) simulators. The junctionless structure is adopted because of the simple fabrication process without formation of junctions, lower leakage current characteristics, low short channel effects (SCE) characteristics, and nearly ideal switching performances. In addition, the GAA nanowire architecture enhances the device characteristics by increasing gate dominance, decreasing the bulk-leakage current, and increasing the degree of integration. The gate length (L_G), threshold voltage (V_t), radius of nanowire (R_ch) and doping concentration (N_ch) of the InGaAs channel region which are important for a transistor design optimization processes, are considered the main design variables. The direct-current (DC) with radio-frequency (RF) performance is investigated. The optimally designed InGaAs-based GAA JLFET demonstrated an on-state current (I_on) of 672 A/m, an off-state current (I_off) of 26×10¹¹ A/m, a subthreshold-swing (S) of 61 mV/dec, a maximum cut-off frequency (f_T ) of 23 THz, and a maximum oscillation frequency (f_max) of 75 THz.