@inproceedings{a68a8d0ec27f4027b1e2bb5d4c4b540b,
title = "Design optimization InGaAs/GaAsSb-based heterojunction Gate-all-around (GAA) arch-shaped tunneling field-effect transistor (A-TFET)",
abstract = "The InGaAs/GaAsSb-based heterojunction gate-all-around (GAA) arch-shaped tunneling field-effect transistor (A-TFET) has been designed and optimized by Silvaco ATLAS technology computer-aided design (TCAD) simulators. The proposed device has a GaAs0.35Sb0.65-based p-doped source, In0.7Ga0.3As-based i-doped channel and In0.7Ga0.3As-based n-doped drain. The gate-to-drain length (LGD), height of source region (Hsource) and epitaxially grown thickness of channel (tepi) was selected as design optimization variables of InGaAs/GaAsSb-based GAA A-TFET.",
keywords = "Arch-shaped, Gate-all-around (GAA), InGaAs/GaAsSb-based, TFET",
author = "Seo, \{Jae Hwa\} and Yoon, \{Young Jun\} and Lee, \{Hwan Gi\} and Kang, \{In Man\}",
note = "Publisher Copyright: {\textcopyright} 2018 Institute of Electronics and Information Engineers.; 17th International Conference on Electronics, Information and Communication, ICEIC 2018 ; Conference date: 24-01-2018 Through 27-01-2018",
year = "2018",
month = apr,
day = "2",
doi = "10.23919/ELINFOCOM.2018.8330638",
language = "English",
series = "International Conference on Electronics, Information and Communication, ICEIC 2018",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1--2",
booktitle = "International Conference on Electronics, Information and Communication, ICEIC 2018",
address = "United States",
}