Design Optimization of a 4-2 Compressor for Low-cost Approximate Multipliers

Approximate computing can enhance hardware efficiency for error-tolerant applications. This technique can be applied to basic arithmetic operations such as multiplication. Approximate multiplication is generally implemented using several approximate compressors. In this paper, we propose an optimized 4-2 approximate compressor based on an existing compressor. We elaborate Boolean expressions for the compressor to replace the original gates with compound gates that reduce the hardware resource consumption. Compared to the original design, the optimized compressor's area and power are improved by 62.5% and 65.7%, respectively. When the proposed compressor is applied to multiplier configurations, it reduces the area and power by at least 13%. Additionally, our simulation results show that it achieves better hardware performance than other approximate compressors.