Design optimization of silicon-based junctionless fin-type field-effect transistors for low standby power technology

Recently, the junctionless (JL) transistors realized by a single-type doping process have attracted attention instead of the conventional metal-oxide-semiconductor field-effect transistors (MOSFET). The JL transistor can overcome MOSFET's problems such as the thermal budget and short-channel effect. Thus, the JL transistor is considered as great alternative device for a next generation low standby power silicon system. In this paper, the JL FinFET was simulated with a three dimensional (3D) technology computer-aided design (TCAD) simulator and optimized for DC characteristics according to device dimension and doping concentration. The design variables were the fin width (W_fin), fin height (H_fin), and doping concentration (D_ch). After the optimization of DC characteristics, RF characteristics of JL FinFET were also extracted.