Design optimization of vertical double-gate tunneling field-effect transistors

Young Jun Yoon; Sung Yun Woo; Jae Hwa Seo; Jae Sung Lee; Yun Soo Park; Jung Hee Lee; In Man Kang

doi:10.3938/jkps.61.1679

Design optimization of vertical double-gate tunneling field-effect transistors

Young Jun Yoon, Sung Yun Woo, Jae Hwa Seo, Jae Sung Lee, Yun Soo Park, Jung Hee Lee, In Man Kang

School of Electronics Engineering

Kyungpook National University

Research output: Contribution to journal › Article › peer-review

5 Scopus citations

Abstract

In this work, design optimization of vertical double-gate (VDG) tunneling field-effect transistors (TFETs) with hetero-gate dielectric (HG) materials has been performed. High-k materials such as Si₃N₄, HfO₂, and ZrO₂ were used for the HG structure. The optimized parameters for maximizing the device performances were the length of the high-k material (L_high-k) and the thickness of silicon channel (t_Si). For HfO₂, the subthreshold swing (SS) and on-current were optimized at a L_high-k of 11 nm and a t_Si of 5 nm. The optimized device had an on-current (I_on) of 151 μA/μm and a SS of 46. 6 mV/dec. In addition, to improve the on-current level of the optimized device, we inserted a thin n-doped layer into the channel near the source side, and we analyzed the performance. The on-current level of the device with an n-doped layer was nearly double that of the device without an n-doped layer.

Original language	English
Pages (from-to)	1679-1682
Number of pages	4
Journal	Journal of the Korean Physical Society
Volume	61
Issue number	10
DOIs	https://doi.org/10.3938/jkps.61.1679
State	Published - Dec 2012

Keywords

Band-to-band tunneling
Double gate (DG)
High-k dielectric
n-doped layer
Tunnel field-effect transistor

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10.3938/jkps.61.1679

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@article{e113ad9611674847b69d0e65f1ad0cf8,

title = "Design optimization of vertical double-gate tunneling field-effect transistors",

abstract = "In this work, design optimization of vertical double-gate (VDG) tunneling field-effect transistors (TFETs) with hetero-gate dielectric (HG) materials has been performed. High-k materials such as Si3N4, HfO2, and ZrO2 were used for the HG structure. The optimized parameters for maximizing the device performances were the length of the high-k material (Lhigh-k) and the thickness of silicon channel (tSi). For HfO2, the subthreshold swing (SS) and on-current were optimized at a Lhigh-k of 11 nm and a tSi of 5 nm. The optimized device had an on-current (Ion) of 151 μA/μm and a SS of 46. 6 mV/dec. In addition, to improve the on-current level of the optimized device, we inserted a thin n-doped layer into the channel near the source side, and we analyzed the performance. The on-current level of the device with an n-doped layer was nearly double that of the device without an n-doped layer.",

keywords = "Band-to-band tunneling, Double gate (DG), High-k dielectric, n-doped layer, Tunnel field-effect transistor",

author = "Yoon, {Young Jun} and Woo, {Sung Yun} and Seo, {Jae Hwa} and Lee, {Jae Sung} and Park, {Yun Soo} and Lee, {Jung Hee} and Kang, {In Man}",

year = "2012",

month = dec,

doi = "10.3938/jkps.61.1679",

language = "English",

volume = "61",

pages = "1679--1682",

journal = "Journal of the Korean Physical Society",

issn = "0374-4884",

publisher = "Korean Physical Society",

number = "10",

}

TY - JOUR

T1 - Design optimization of vertical double-gate tunneling field-effect transistors

AU - Yoon, Young Jun

AU - Woo, Sung Yun

AU - Seo, Jae Hwa

AU - Lee, Jae Sung

AU - Park, Yun Soo

AU - Lee, Jung Hee

AU - Kang, In Man

PY - 2012/12

Y1 - 2012/12

N2 - In this work, design optimization of vertical double-gate (VDG) tunneling field-effect transistors (TFETs) with hetero-gate dielectric (HG) materials has been performed. High-k materials such as Si3N4, HfO2, and ZrO2 were used for the HG structure. The optimized parameters for maximizing the device performances were the length of the high-k material (Lhigh-k) and the thickness of silicon channel (tSi). For HfO2, the subthreshold swing (SS) and on-current were optimized at a Lhigh-k of 11 nm and a tSi of 5 nm. The optimized device had an on-current (Ion) of 151 μA/μm and a SS of 46. 6 mV/dec. In addition, to improve the on-current level of the optimized device, we inserted a thin n-doped layer into the channel near the source side, and we analyzed the performance. The on-current level of the device with an n-doped layer was nearly double that of the device without an n-doped layer.

AB - In this work, design optimization of vertical double-gate (VDG) tunneling field-effect transistors (TFETs) with hetero-gate dielectric (HG) materials has been performed. High-k materials such as Si3N4, HfO2, and ZrO2 were used for the HG structure. The optimized parameters for maximizing the device performances were the length of the high-k material (Lhigh-k) and the thickness of silicon channel (tSi). For HfO2, the subthreshold swing (SS) and on-current were optimized at a Lhigh-k of 11 nm and a tSi of 5 nm. The optimized device had an on-current (Ion) of 151 μA/μm and a SS of 46. 6 mV/dec. In addition, to improve the on-current level of the optimized device, we inserted a thin n-doped layer into the channel near the source side, and we analyzed the performance. The on-current level of the device with an n-doped layer was nearly double that of the device without an n-doped layer.

KW - Band-to-band tunneling

KW - Double gate (DG)

KW - High-k dielectric

KW - n-doped layer

KW - Tunnel field-effect transistor

UR - http://www.scopus.com/inward/record.url?scp=84870780453&partnerID=8YFLogxK

U2 - 10.3938/jkps.61.1679

DO - 10.3938/jkps.61.1679

M3 - Article

AN - SCOPUS:84870780453

SN - 0374-4884

VL - 61

SP - 1679

EP - 1682

JO - Journal of the Korean Physical Society

JF - Journal of the Korean Physical Society

IS - 10

ER -

Design optimization of vertical double-gate tunneling field-effect transistors

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