TY - JOUR
T1 - Design Technology Co-Optimization and Time-Efficient Verification for Enhanced Pin Accessibility in the Post-3-nm Node
AU - Jeong, Jaehoon
AU - Shin, Yunjeong
AU - Lee, Hyundong
AU - Ko, Jonghyun
AU - Kim, Jongbeom
AU - Song, Taigon
N1 - Publisher Copyright:
© 2013 IEEE.
PY - 2024
Y1 - 2024
N2 - As the technology nodes approach 3 nm and beyond, nanosheet FETs (NSFETs) are replacing FinFETs. However, despite the migration of devices from FinFETs to NSFETs, few studies report the impact of NSFETs in the digital VLSI's perspective. In this paper, we present a study of how the latest device technology, back end of line (BEOL), and the designs of NSFETs aid each other for enhanced pin accessibility in layout and standard cell library design for less routing congestion and low power consumption. For this objective, 1) we discuss five layout design methodologies that are co-optimized with device technology to tackle the pin accessibility issues that arise in standard cell designs in extremely-low routing resource environments (e.g., 4 Signal Tracks), 2) we introduce pin accessibility analysis procedures before chip P&R, and 3) we report how local trench contact (LTC) helps in reducing cell tracks for 5 track cells and less. Using our methodology, we improve design metrics such as power consumption, total area, and wirelength by 11.0%, 13.2%, and 16.0%, respectively in full-chip scale designs. By our study, we expect the routing congestion issues that additionally occur in advanced technology nodes to be handled and better full-chip designs to be done in 3 nm and beyond.
AB - As the technology nodes approach 3 nm and beyond, nanosheet FETs (NSFETs) are replacing FinFETs. However, despite the migration of devices from FinFETs to NSFETs, few studies report the impact of NSFETs in the digital VLSI's perspective. In this paper, we present a study of how the latest device technology, back end of line (BEOL), and the designs of NSFETs aid each other for enhanced pin accessibility in layout and standard cell library design for less routing congestion and low power consumption. For this objective, 1) we discuss five layout design methodologies that are co-optimized with device technology to tackle the pin accessibility issues that arise in standard cell designs in extremely-low routing resource environments (e.g., 4 Signal Tracks), 2) we introduce pin accessibility analysis procedures before chip P&R, and 3) we report how local trench contact (LTC) helps in reducing cell tracks for 5 track cells and less. Using our methodology, we improve design metrics such as power consumption, total area, and wirelength by 11.0%, 13.2%, and 16.0%, respectively in full-chip scale designs. By our study, we expect the routing congestion issues that additionally occur in advanced technology nodes to be handled and better full-chip designs to be done in 3 nm and beyond.
KW - library
KW - nanosheet
KW - NSFET
KW - pin optimization
KW - standard cell layout
UR - http://www.scopus.com/inward/record.url?scp=85199183218&partnerID=8YFLogxK
U2 - 10.1109/ACCESS.2024.3427332
DO - 10.1109/ACCESS.2024.3427332
M3 - Article
AN - SCOPUS:85199183218
SN - 2169-3536
VL - 12
SP - 97557
EP - 97571
JO - IEEE Access
JF - IEEE Access
ER -