Development of a digital FPLL ASIC for GA HDTV receivers

Dong Seog Han; Myeong Hwan Lee; Kil Houm Park

Development of a digital FPLL ASIC for GA HDTV receivers

Dong Seog Han, Myeong Hwan Lee, Kil Houm Park

School of Electronics Engineering

Kyungpook National University

Research output: Contribution to journal › Conference article › peer-review

Abstract

In this paper, we propose a new digital carrier recovery loop architecture for the Grand Alliance (GA) HDTV system. We have developed an ASIC based on the new architecture. The developed ASIC has the gate count of 60 K with a gate array technology that features on 0.5 μm, 3.3 V and 2-metal-layers technology. The pull-in range of the proposed architecture is about ±250 KHz with OdB carrier-to-noise ratio (CNR).

Original language	English
Pages (from-to)	360-361
Number of pages	2
Journal	Digest of Technical Papers - IEEE International Conference on Consumer Electronics
State	Published - 1997
Event	Proceedings of the 1997 16th International Conference on Consumer Electronics, ICCE - Rosemont, IL, USA Duration: 11 Jun 1997 → 13 Jun 1997

Cite this

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title = "Development of a digital FPLL ASIC for GA HDTV receivers",

abstract = "In this paper, we propose a new digital carrier recovery loop architecture for the Grand Alliance (GA) HDTV system. We have developed an ASIC based on the new architecture. The developed ASIC has the gate count of 60 K with a gate array technology that features on 0.5 μm, 3.3 V and 2-metal-layers technology. The pull-in range of the proposed architecture is about ±250 KHz with OdB carrier-to-noise ratio (CNR).",

author = "Han, \{Dong Seog\} and Lee, \{Myeong Hwan\} and Park, \{Kil Houm\}",

year = "1997",

language = "English",

pages = "360--361",

journal = "Digest of Technical Papers - IEEE International Conference on Consumer Electronics",

issn = "0747-668X",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1997 16th International Conference on Consumer Electronics, ICCE ; Conference date: 11-06-1997 Through 13-06-1997",

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T1 - Development of a digital FPLL ASIC for GA HDTV receivers

AU - Han, Dong Seog

AU - Lee, Myeong Hwan

AU - Park, Kil Houm

PY - 1997

Y1 - 1997

N2 - In this paper, we propose a new digital carrier recovery loop architecture for the Grand Alliance (GA) HDTV system. We have developed an ASIC based on the new architecture. The developed ASIC has the gate count of 60 K with a gate array technology that features on 0.5 μm, 3.3 V and 2-metal-layers technology. The pull-in range of the proposed architecture is about ±250 KHz with OdB carrier-to-noise ratio (CNR).

AB - In this paper, we propose a new digital carrier recovery loop architecture for the Grand Alliance (GA) HDTV system. We have developed an ASIC based on the new architecture. The developed ASIC has the gate count of 60 K with a gate array technology that features on 0.5 μm, 3.3 V and 2-metal-layers technology. The pull-in range of the proposed architecture is about ±250 KHz with OdB carrier-to-noise ratio (CNR).

UR - https://www.scopus.com/pages/publications/0031353061

M3 - Conference article

AN - SCOPUS:0031353061

SN - 0747-668X

SP - 360

EP - 361

JO - Digest of Technical Papers - IEEE International Conference on Consumer Electronics

JF - Digest of Technical Papers - IEEE International Conference on Consumer Electronics

T2 - Proceedings of the 1997 16th International Conference on Consumer Electronics, ICCE

Y2 - 11 June 1997 through 13 June 1997

ER -

Development of a digital FPLL ASIC for GA HDTV receivers

Abstract

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