Effect of a two-step recess process using atomic layer etching on the performance of In0.52Al0.48As/In0.53 Ga0.47As p-HEMTs

Tae Woo Kim, Dae Hyun Kim, Sang Duk Park, Geun Young Yeom, Byeong Ok Lim, Jin Koo Rhee, Jae Hyung Jang, Jong In Song

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

The characteristics of 0.15-μm InAlAs/InGaAs pseudomorphic high-electron mobility transistors (p-HEMTs) that were fabricated using the Ne-based atomic layer etching (ALET) technology and the Ar-based conventional reactive ion etching (RIE) technology were investigated. As compared with the RIE, the ALET used a much lower plasma energy and thus produced much lower plasma-induced damages to the surface and bulk of the In0.52Al0.48As barrier and showed a much higher etch selectivity (∼70) of the InP spacer against the In0.52Al0.48As barrier. The 0.15-μm InAlAs/ InGaAs p-HEMTs that were fabricated using the ALET exhibited improved GM,max (1.38 S/mm), ION/IOFF(1.18 × 104), drain-induced barrier lowering (80 mV/V), threshold voltage uniformity (Vth,avg = -190 mV and σ = 15 mV), and fT (233 GHz), mainly due to the extremely low plasma-induced damage in the Schottky gate area.

Original languageEnglish
Pages (from-to)1086-1088
Number of pages3
JournalIEEE Electron Device Letters
Volume28
Issue number12
DOIs
StatePublished - Dec 2007

Keywords

  • Atomic layer deposition
  • Atomic layer etching (ALET)
  • Electron mobility
  • HEMT circuits
  • High electron mobility transistors
  • I/I ratio
  • Pseudomorphic high-electron mobility transistor (p-HEMT)
  • Subthreshold slope
  • drain-induced barrier lowering (DIBL)

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