Effect of electric fringe-field on low-power and radio-frequency performances of sub-10 nm junctionless transistors with hetero-dielectric spacer structure

In this work, we present a hetero-dielectric spacer structure for the realization of sub-10 nm germanium (Ge)-based multiple-gate junctionless transistors (JLTs) with exceptional low power (LP) and radio-frequency (RF) performances. The hetero-dielectric spacer structure consists of SiO₂ and high-k dielectric HfO₂. The HfO₂ in the hetero-dielectric spacer induces a considerable electric fringe-field owing to high relative permittivity (Ε_r). The high electric fringe-field improves the gate controllability and suppresses the drain-induced barrier lowering (DIBL) owing to an extended effective channel length (Le_{ff_ch}) and an increased potential barrier height. JLTs with hetero-dielectric spacers have smaller subthreshold swings (S) and lower off-state currents (I_off) than JLT with single-dielectric spacer SiO₂. The effect of the hetero-dielectric spacer on LP performance is changed by the length of the HfO₂ in the hetero-dielectric spacer (LHfO₂). An optimized JLT with an LHfO₂ of 15 nm exhibits outstanding LP performance including an S of 62.4 mV/dec and an I_off of 1.16 pA/Μm. Further, the SiO₂ in the hetero-dielectric spacer decreases the out-fringe capacitance (C_of) that is increased by the HfO₂ in the spacer; the decrease achieves a lower gate capacitance (C_gg). Therefore, a JLT with an LH_fO2 of 15 nm obtains a higher cut-off frequency (f_T) of 477 GHz and a shorter intrinsic delay time (τ) of 1.38 ps, compared to a JLT with a single-spacer HfO₂. Both the LP and RF performances of the proposed JLTs are simultaneously enhanced by the hetero-dielectric spacer structure.