TY - GEN
T1 - Enhancing Stochastic Computing using a Novel Hybrid Random Number Generator Integrating LFSR and Halton Sequence
AU - Lee, Donghui
AU - Baik, Junhyuk
AU - Kim, Yongtae
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - This paper presents a new approach to address the increased hardware complexity and power demands associated with using multiple random number generator (RNG) in stochastic computing (SC). We propose a novel hybrid RNG, which combines a linear feedback shift register (LFSR) and a Halton sequence generator, to facilitate efficient generation of random number sequences in SC. Implemented in a 65- nm CMOS technology, our hybrid RNG yields up to 18% and 30% enhancements in area and power, respectively, compared to the traditional LFSR-based equivalent. Further, the proposed RNG's efficacy is demonstrated through its incorporation in SC-based Robert cross-edge detector algorithm, yielding reductions in area and power by 28% and 35%, respectively, while preserving superior processing quality.
AB - This paper presents a new approach to address the increased hardware complexity and power demands associated with using multiple random number generator (RNG) in stochastic computing (SC). We propose a novel hybrid RNG, which combines a linear feedback shift register (LFSR) and a Halton sequence generator, to facilitate efficient generation of random number sequences in SC. Implemented in a 65- nm CMOS technology, our hybrid RNG yields up to 18% and 30% enhancements in area and power, respectively, compared to the traditional LFSR-based equivalent. Further, the proposed RNG's efficacy is demonstrated through its incorporation in SC-based Robert cross-edge detector algorithm, yielding reductions in area and power by 28% and 35%, respectively, while preserving superior processing quality.
KW - Halton sequence
KW - linear feedback shift register (LFSR)
KW - random number generator (RNG)
KW - stochastic computing (SC)
UR - http://www.scopus.com/inward/record.url?scp=85184819798&partnerID=8YFLogxK
U2 - 10.1109/ISOCC59558.2023.10396483
DO - 10.1109/ISOCC59558.2023.10396483
M3 - Conference contribution
AN - SCOPUS:85184819798
T3 - Proceedings - International SoC Design Conference 2023, ISOCC 2023
SP - 7
EP - 8
BT - Proceedings - International SoC Design Conference 2023, ISOCC 2023
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 20th International SoC Design Conference, ISOCC 2023
Y2 - 25 October 2023 through 28 October 2023
ER -