Experimental N-style two-transistor eDRAM in logic CMOS technology

Hritom Das; Sivasundar Manisankar; Weijie Cheng; Yeonbae Chung

doi:10.1109/EDSSC.2015.7285053

Experimental N-style two-transistor eDRAM in logic CMOS technology

Hritom Das, Sivasundar Manisankar, Weijie Cheng, Yeonbae Chung

School of Electronics Engineering

Kyungpook National University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

In this work, we demonstrate an experimental eDRAM utilizing logic-compatible N-style 2T gain cell on 130 nm CMOS technology. The memory bit-cell consists of a high-V_TH write NMOS and a standard-V_TH read NMOS. Combination of a low off-leakage device for write and a high mobility device for read provides much improved retention time and read performance in a compact bit area. The embedded macro operates with 32-kbit density, SRAM-like I/O interface and self-timed 128-row refresh. Measured retention time in typical 32-kbit dies at 1.2 V and room temperature exhibits an average of 2.1 ms.

Original language	English
Title of host publication	Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	75-78
Number of pages	4
ISBN (Electronic)	9781479983636
DOIs	https://doi.org/10.1109/EDSSC.2015.7285053
State	Published - 30 Sep 2015
Event	11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015 - Singapore, Singapore Duration: 1 Jun 2015 → 4 Jun 2015

Publication series

Name	Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015

Conference

Conference	11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
Country/Territory	Singapore
City	Singapore
Period	1/06/15 → 4/06/15

Keywords

embedded DRAM
gain cell
Memory
SoC

Access to Document

10.1109/EDSSC.2015.7285053

Cite this

Das, H., Manisankar, S., Cheng, W., & Chung, Y. (2015). Experimental N-style two-transistor eDRAM in logic CMOS technology. In Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015 (pp. 75-78). Article 7285053 (Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2015.7285053

Das, Hritom ; Manisankar, Sivasundar ; Cheng, Weijie et al. / Experimental N-style two-transistor eDRAM in logic CMOS technology. Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 75-78 (Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015).

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title = "Experimental N-style two-transistor eDRAM in logic CMOS technology",

abstract = "In this work, we demonstrate an experimental eDRAM utilizing logic-compatible N-style 2T gain cell on 130 nm CMOS technology. The memory bit-cell consists of a high-VTH write NMOS and a standard-VTH read NMOS. Combination of a low off-leakage device for write and a high mobility device for read provides much improved retention time and read performance in a compact bit area. The embedded macro operates with 32-kbit density, SRAM-like I/O interface and self-timed 128-row refresh. Measured retention time in typical 32-kbit dies at 1.2 V and room temperature exhibits an average of 2.1 ms.",

keywords = "embedded DRAM, gain cell, Memory, SoC",

author = "Hritom Das and Sivasundar Manisankar and Weijie Cheng and Yeonbae Chung",

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language = "English",

series = "Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015",

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Das, H, Manisankar, S, Cheng, W & Chung, Y 2015, Experimental N-style two-transistor eDRAM in logic CMOS technology. in Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015., 7285053, Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015, Institute of Electrical and Electronics Engineers Inc., pp. 75-78, 11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015, Singapore, Singapore, 1/06/15. https://doi.org/10.1109/EDSSC.2015.7285053

Experimental N-style two-transistor eDRAM in logic CMOS technology. / Das, Hritom; Manisankar, Sivasundar; Cheng, Weijie et al.
Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 75-78 7285053 (Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Manisankar, Sivasundar

AU - Cheng, Weijie

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PY - 2015/9/30

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N2 - In this work, we demonstrate an experimental eDRAM utilizing logic-compatible N-style 2T gain cell on 130 nm CMOS technology. The memory bit-cell consists of a high-VTH write NMOS and a standard-VTH read NMOS. Combination of a low off-leakage device for write and a high mobility device for read provides much improved retention time and read performance in a compact bit area. The embedded macro operates with 32-kbit density, SRAM-like I/O interface and self-timed 128-row refresh. Measured retention time in typical 32-kbit dies at 1.2 V and room temperature exhibits an average of 2.1 ms.

AB - In this work, we demonstrate an experimental eDRAM utilizing logic-compatible N-style 2T gain cell on 130 nm CMOS technology. The memory bit-cell consists of a high-VTH write NMOS and a standard-VTH read NMOS. Combination of a low off-leakage device for write and a high mobility device for read provides much improved retention time and read performance in a compact bit area. The embedded macro operates with 32-kbit density, SRAM-like I/O interface and self-timed 128-row refresh. Measured retention time in typical 32-kbit dies at 1.2 V and room temperature exhibits an average of 2.1 ms.

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KW - SoC

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T3 - Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015

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BT - Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015

PB - Institute of Electrical and Electronics Engineers Inc.

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Das H, Manisankar S, Cheng W, Chung Y. Experimental N-style two-transistor eDRAM in logic CMOS technology. In Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 75-78. 7285053. (Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015). doi: 10.1109/EDSSC.2015.7285053

Experimental N-style two-transistor eDRAM in logic CMOS technology

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