Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction

Kiyung Kim; Sunmean Kim; Yongsu Lee; Daeyeon Kim; So Young Kim; Seokhyeong Kang; Byoung Hun Lee

doi:10.1109/ISMVL49045.2020.00-13

Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction

Kiyung Kim, Sunmean Kim, Yongsu Lee, Daeyeon Kim, So Young Kim, Seokhyeong Kang, Byoung Hun Lee

School of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

8 Scopus citations

Abstract

Ternary logic is more power-efficient than binary logic because of lower device count required to perform the same logic functions. Its benefits become more pronounced in highly scaled systems where most power consumption occurs at the interconnect portion. We examined the benefits of ternary logic including the impacts of interconnect length reduction using a realistic ternary device model. The standard cell layouts of ternary SUM, NCARRY, NANY, and PROD gates are designed using balanced ternary logic and multi-threshold graphene barrister (MTGB). The interconnect wire length of the 5-trit arithmetic logic unit is reduced by ~37 % and this reduction rate is maintained even in more complex circuits.

Original language	English
Title of host publication	Proceedings - 2020 IEEE 50th International Symposium on Multiple-Valued Logic, ISMVL 2020
Publisher	IEEE Computer Society
Pages	155-158
Number of pages	4
ISBN (Electronic)	9781728154060
DOIs	https://doi.org/10.1109/ISMVL49045.2020.00-13
State	Published - Nov 2020
Event	50th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2020 - Miyazaki, Japan Duration: 9 Nov 2020 → 11 Nov 2020

Publication series

Name	Proceedings of The International Symposium on Multiple-Valued Logic
Volume	2020-November
ISSN (Print)	0195-623X

Conference

Conference	50th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2020
Country/Territory	Japan
City	Miyazaki
Period	9/11/20 → 11/11/20

Keywords

interconnect length
low power technology
ternary logic

Access to Document

10.1109/ISMVL49045.2020.00-13

Cite this

Kim, K., Kim, S., Lee, Y., Kim, D., Kim, S. Y., Kang, S., & Lee, B. H. (2020). Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction. In Proceedings - 2020 IEEE 50th International Symposium on Multiple-Valued Logic, ISMVL 2020 (pp. 155-158). Article 9308509 (Proceedings of The International Symposium on Multiple-Valued Logic; Vol. 2020-November). IEEE Computer Society. https://doi.org/10.1109/ISMVL49045.2020.00-13

@inproceedings{4bb7d5af3548444b8176c5e5d6bfd158,

title = "Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction",

abstract = "Ternary logic is more power-efficient than binary logic because of lower device count required to perform the same logic functions. Its benefits become more pronounced in highly scaled systems where most power consumption occurs at the interconnect portion. We examined the benefits of ternary logic including the impacts of interconnect length reduction using a realistic ternary device model. The standard cell layouts of ternary SUM, NCARRY, NANY, and PROD gates are designed using balanced ternary logic and multi-threshold graphene barrister (MTGB). The interconnect wire length of the 5-trit arithmetic logic unit is reduced by ~37 % and this reduction rate is maintained even in more complex circuits.",

keywords = "interconnect length, low power technology, ternary logic",

author = "Kiyung Kim and Sunmean Kim and Yongsu Lee and Daeyeon Kim and Kim, {So Young} and Seokhyeong Kang and Lee, {Byoung Hun}",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 50th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2020 ; Conference date: 09-11-2020 Through 11-11-2020",

year = "2020",

month = nov,

doi = "10.1109/ISMVL49045.2020.00-13",

language = "English",

series = "Proceedings of The International Symposium on Multiple-Valued Logic",

publisher = "IEEE Computer Society",

pages = "155--158",

booktitle = "Proceedings - 2020 IEEE 50th International Symposium on Multiple-Valued Logic, ISMVL 2020",

address = "United States",

}

Kim, K, Kim, S, Lee, Y, Kim, D, Kim, SY, Kang, S & Lee, BH 2020, Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction. in Proceedings - 2020 IEEE 50th International Symposium on Multiple-Valued Logic, ISMVL 2020., 9308509, Proceedings of The International Symposium on Multiple-Valued Logic, vol. 2020-November, IEEE Computer Society, pp. 155-158, 50th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2020, Miyazaki, Japan, 9/11/20. https://doi.org/10.1109/ISMVL49045.2020.00-13

Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction. / Kim, Kiyung; Kim, Sunmean; Lee, Yongsu et al.
Proceedings - 2020 IEEE 50th International Symposium on Multiple-Valued Logic, ISMVL 2020. IEEE Computer Society, 2020. p. 155-158 9308509 (Proceedings of The International Symposium on Multiple-Valued Logic; Vol. 2020-November).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction

AU - Kim, Kiyung

AU - Kim, Sunmean

AU - Lee, Yongsu

AU - Kim, Daeyeon

AU - Kim, So Young

AU - Kang, Seokhyeong

AU - Lee, Byoung Hun

PY - 2020/11

Y1 - 2020/11

N2 - Ternary logic is more power-efficient than binary logic because of lower device count required to perform the same logic functions. Its benefits become more pronounced in highly scaled systems where most power consumption occurs at the interconnect portion. We examined the benefits of ternary logic including the impacts of interconnect length reduction using a realistic ternary device model. The standard cell layouts of ternary SUM, NCARRY, NANY, and PROD gates are designed using balanced ternary logic and multi-threshold graphene barrister (MTGB). The interconnect wire length of the 5-trit arithmetic logic unit is reduced by ~37 % and this reduction rate is maintained even in more complex circuits.

AB - Ternary logic is more power-efficient than binary logic because of lower device count required to perform the same logic functions. Its benefits become more pronounced in highly scaled systems where most power consumption occurs at the interconnect portion. We examined the benefits of ternary logic including the impacts of interconnect length reduction using a realistic ternary device model. The standard cell layouts of ternary SUM, NCARRY, NANY, and PROD gates are designed using balanced ternary logic and multi-threshold graphene barrister (MTGB). The interconnect wire length of the 5-trit arithmetic logic unit is reduced by ~37 % and this reduction rate is maintained even in more complex circuits.

KW - interconnect length

KW - low power technology

KW - ternary logic

UR - http://www.scopus.com/inward/record.url?scp=85099778089&partnerID=8YFLogxK

U2 - 10.1109/ISMVL49045.2020.00-13

DO - 10.1109/ISMVL49045.2020.00-13

M3 - Conference contribution

AN - SCOPUS:85099778089

T3 - Proceedings of The International Symposium on Multiple-Valued Logic

SP - 155

EP - 158

BT - Proceedings - 2020 IEEE 50th International Symposium on Multiple-Valued Logic, ISMVL 2020

PB - IEEE Computer Society

T2 - 50th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2020

Y2 - 9 November 2020 through 11 November 2020

ER -

Kim K, Kim S, Lee Y, Kim D, Kim SY, Kang S et al. Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction. In Proceedings - 2020 IEEE 50th International Symposium on Multiple-Valued Logic, ISMVL 2020. IEEE Computer Society. 2020. p. 155-158. 9308509. (Proceedings of The International Symposium on Multiple-Valued Logic). doi: 10.1109/ISMVL49045.2020.00-13

Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction

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